Toshiba T1200 - A.5 I;O DECODER; C.5 I;O DECODER

C" 5 I/O DBCODBR
This is the circuit that decodes the I/O address signals to
select the various devices such as 82CS9, 82C37, Bus
Controller G"A", BIOS ROM, and Back-up RAM, etc""
I/O address of each device above mentioned is as followsJ
82C37
82CS9
82CS3
DMA Page Reg"
NMI Mask Reg"
PIO
Machine Reg"
I/O address(Hex)
OOO-OIF
020-03F
040-0SF
080-09F
OAO-OBF
060-07F
OEO-OE4
Signal name
DMACSO
INTCSO
TIMCSO
PAGWRO
NMICSO
PPICSO
MCRCSO
In the DMA mode, chip select signal should not be output,
and therefore, HLDAI signal must be set to "1" (See c-s Pin
37) "
Each signal is described by the logical mode as followsJ
DMACSO = A9"A8"A7"A6"AS"HLDA
INTCSO = A9"A8"A7"A6"AS"HLDA
TIMCSO = A9"A8"A7"A6"AS"HLDA
PAGWRO = A9"A8"A7"A6"AS"IOWO"HLDA
NMICSO = A9"A8"A7"A6"AS"IOWO"HLDA
PPICSO = A9"A8"A7"A6"AS"HLDA
MCRCSO = A9"A8"A7"A6"AS"A4"A3"(A2+A2"Al"AO) "HLDA
C - 8