Toshiba TECRA 9100 Series - Page 25

1.2 System Unit Block Diagram 1 Hardware Overview
TECRA 9100 Maintenance Manual (960-347) 1-11
− Docking station interface
Q switch control, reset control
− External device interface
− FDD/IDE hot plugging and removal control
− Slim Select Bay interface
 Firmware Hub (FWH)
• One Intel 82802AB8 is used.
• This gate array has the following features:
− Intel platform compatibility
− Firmware hub hardware interface mode
− Industry-standard packages
− Two configurable interfaces
− 4Mbits of flash memory for platform code/data nonvolatile storage
− Address/Address-Multiplexed (A/A Mux) interface/mode
− Case temperature operating range
− Vcc: 3.3V ± 0.3V
− Vpp: 3.3V and 12V for fast programming (80 hours maximum)
• 4Mbits of flash memory are used as shown below:
− 64KB are used for VGA-BIOS.
− 192KB are used for system BIOS.
− 8KB are used for plug and play data area.
− 8KB are used for password security.
− 16KB are used for boot strap.
− 64KB are used for ACPI P code.
− 64KB are used for LOGO.
− 64KB are reserved for LAN BIOS.
− 32KB are reserved.