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Toshiba TECRA 9100 Series - Page 26

Toshiba TECRA 9100 Series
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1 Hardware Overview 1.2 System Unit Block Diagram
1-12 TECRA 9100 Maintenance Manual (960-347)
Display Controller
One S3 Tristar 64C86C584 chip is used. The video controller incorporates, graphics
accelerator, video accelerator.
1.85 volt (core)/3.3 volt (interface) operation.
Connected to AGP bus
3D accelerator function.
Video RAM, VRAM 16MB is integrated in the VGAC
Sound Controller
One Yamaha YMF753 chip is used.
SW sound
EC/KBC (Embedded Controller/Keyboard Controller)
One Mitsubishi M306K7F8LRLPC micon chip functions as both EC and
KBC.
EC
This controller controls the following functions:
Power supply sequence
Thermal conditions
LEDs
Beep
Device ON/OFF
Fan speed
Universal I/O port
Docker Docking Sequence
Battery capacity check
Forced reset
Flash rewriting
EC interface
I
2
C communication
EC access
Slim Select Bay Control
KBC
This controller has the following functions:
Scan controller to check status of keyboard matrix
Interface controller between the keyboard scan controller and the system
Control of switching and simultaneous operation of the accupoint/external
PS/2 mouse and of the internal keyboard/external PS/2 keyboard

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