u-blox NINA-W1 series - Architecture; Block Diagrams

NINA-W1 series - System Integration Manual
UBX-17005730 - R07 System description Page 6 of 47
1.2 Architecture
1.2.1 Block diagrams
Figure 1: Block diagram of NINA-W13 series
Figure 2: Block diagram of NINA-W15 series
Flash (16Mbit)
Linear voltage regulators
RF
ROM
Wi
-Fi
baseband
IO Buffers
2xXtensa 32-bit LX6 MCU
SRAM (4Mbit)
Cryptographics
hardware
accelerations
Antenna
(NINA-W132)
PLL
Quad SPI
VCC_IO
VCC (3.0
-3.6V)
40 MHz
Reset
UART
RMII
EFUSE
GPIO
BPF
ANT (NINA-
W131)
Flash (16Mbit)
Linear voltage regulators
RF
ROM
Wi
-
Fi baseband
IO Buffers
2xXtensa 32-bit LX6 MCU
SRAM (4Mbit)
Cryptographics
hardware
accelerations
Antenna
(NINA-W152)
PLL
Quad SPI
VCC_IO
VCC (3.0
- 3.6V)
40 MHz
Reset
UART
RMII
EFUSE
GPIO
BPF
ANT (NINA-
W151)
Bluetooth
baseband