Vector 4 - Page 116

VECTOR 4
TECHNICAL INFORMATION
.9 HOW THE EXPANSION SLOTS ARE CONFIGURED
Summary: The SBC has three expansion slots which use a modified
S-100 protocol. This protocol (V-100) requires that the additional
boards use regulated power. The Disk Controller Board uses one of
the expansion slots leaving two slots available for future use.
The Expansion Slots are directly connected to four 74LS244 chips. These chips act
as a buffer for all signals which move between the V-100 and the CPU/Data
Address Buses. Exhibit II-3 shows how these SBC Buses relate to the other two
SBC Buses: Multiplexed Address Bus and the I/O Data Bus.
The I/0O Data Bus signals are routed through the I/O Data Bus Transceiver. This
chip acts as a "Directional™ logic gate for I/O access activity. i.e. it selects
between those devices using the CPU Data Bus and those I/O devices using the I/0O
Data Bus. The following chart lists the devices which use each of these buses.
[/O Data Bus CPU Data Bus
- USARTs Expansion Slots
- Parallel Ports PROM
- Timer Address Mapping RAM
- Tone Generator Dynamic RAM
- Video Controller
- 320 Mapping RAM
The complete pin-out of the Expansion Slots is given in Exhibit II-26.
09-01-82 7200-0001 I 5-25