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Vector 4 - Page 34

Vector 4
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VECTOR
4
TECHNICAL
INFORMATION
1.1
HOW
THE
VIDEO
AND
CPU
CYCLES
ARE
COMBINED
Summary:
The
Vector
4
functions
by
using
two
different
cycles
or
time
slots:
YIDEO
and CPU.
Specific
clocking
and
timing
signals
are
generated
so
that
these
cycles
are
maintained.
During
the
Video
cycle
the
data
on
the
address
bus*
is
from
the
Video
System
and
during
the
CPU
time
slot
the
SBC
address
bus
contains
addresses
which
will
be
used
directly
by
the
microprocessor(s).
This
is
done
because
both
these
systems
use
the
same
block
of
RAM
Memory.
Section
1.1-B
describes
each
cyecle
and
discusses
how
the
cycles
relate
to
the
operation
of
the
complete
system.
Exhibit
[I-2
gives
a
pictorial
representation
of
the
timing
cyecles.
4.
Clock
An
oscillator
generates
a
32.64
MHz
(32M)
signal
which
is
sent
to
a
synchronous
counter
(U115),
the
Video
Subsystem
(used
as
a
dot
clock),
and
to
a
group
of
FFs
Wthh
generate
the
clock
for
the
Microprocessors
(Signals
CLOCK
and
CLOCK|
**).
The
synchronous
counter
divides
the
32.64
MHz
signal
into
several
signals
which
are
used
for
particular
timing
functions.
These
latter
timing
signals
along
with
other
31gnals
generated
by
the
clock
subsystem
are
described
below
(See
Tnmmg
Diagram
in
Exhibit
VI-3).
2M,
4M
8M,
16M
These
signals
provide
2MHz,
4MHz,
8MHz
and
16MHz
clock
rates
for
all
the
major
subsystems.
LATCH
This
signal
is
used
within
the
CPU
MUX
Subsystem
(<B8>).
It
clocks
the
lateh
(U34)
so
that
16
bits
of
data
(coming
from
U33
and
U17)
are
multiplexed
to
Data
Bus
lines
0
thru
7.
This
multiplexing
occurs
during
the
T3
state
of
the
YIDEO
Cycle.
The
LATCH
signal
is
also
used
by
the
Video
System
as
a
character
latch.
It
is
routed
to
the
two
video
shift
registers
(KC5>)
where
it
clocks
in
one
row
(a
scan
line
for
one
character
cell)
consisting
of
16
bits.
Its
period
is
lus
with
a
duty
cycle
of
approximately
62
ns.
*
The
Vector
4
uses
several
different
types
of
"Buses".
The
bus
structure
is
shown
in
Exmmt__IL_i
and
described
in
S_ec_tmn_l.z
**
The
"|"
means
the
signal
is
active
LOW.
09-01-82
7200-0001
II1-5