Vector 4 - Page 44

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VECTOR

4

TECHNICAL

INFORMATION

SECTION

I

-

OVERVIEW

OF

THE

RAM/PROM

MEMORY

SYSTEM

Summary:

This

system

provides

the

memory

that

is

used

by

the

CPU

and

Video

Systems.

It

also

contains

the

control

circuitry

which

switches

the

multiplexed

address

lines

during

the

CPU

and

VIDEO

Cycles.

The

RAM/PROM

Memory

System

is

described

by

referencing

the

following

blocks

(subsystems)

from

the

SBC

Block

Diagram

and

Schematics.

Block

Diagram

Number(s)

21

29

29

29

31

32,

34

36,

37

41

41

Schematic

Notation

Bl

B2

B3

B3

B6

B4

B7

B8

Subsystem

Description

Address

Mapping

RAM:

RAM

which

changes

the

Z80B

address

into

a

"Global

Address".

CPU/VIDEQ

MUX

Control;

Multiplexes

the

control

signals

which

enable

the

CPU/VIDEO

Address

MUX

during

the

~eorrect

Cyele

(CPU

or

VIDEO).

CPU/VIDEQ

Address

MUX:

Multiplexes

addresses

generated

by

CPU

and

VIDEO

Systems.

|

Dynamic

RAM

Decoder:

Enables

Dynamic

RAM

through

proper

decoding

of

various

control

signals.

Provides

the

internal

PROM

memory

for

the

Vector

4.

:

Provides

internal

RAM

memory

for

the

Vector

4.

CPU

RAM

Buffers:

Stores

RAM

data

that

is

generated

during

by

the

Microprocessor

Subsystem.

CPU

MUZX

Lateh:

Latches

and

multiplexes

data

stored

in

the

CPU

RAM

Buffers.

The

RAM/PROM

portion

of

the

SBC

Schematic

and

Block

Diagram

is

shown

on

the

next

three

pages.

09-01-82

7200-0001

1

2-1