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2.1

VECTOR

4

TECHNICAL

INFORMATION

HOW

THE

ADDRESS

MAPPING

RAM

AND

ITS

VARIOUS

SUPPLEMENTARY

CONTROL

SUBSYSTEMS

WORK

>

Summary:

In

PART

I

the

concept

of

"Global"

and

"Local

Addresses"

was

presented.

This

section

will

describe

how

the

global

address

is

generated

through

the

use

of

specific

mapping

RAM

chips.

In

order

to

completely

address

a

256

K

block

of

memory

it

is

necessary

to

have

18

address

lines

(218

=

256

K).

The

8088-2

has

18

of

its

possible

20

address

lines

connected.

For

this

reason

these

address

lines

are

sent

directly

to

the

CPU/VIDEO

Address

MUX

where

they

are

multiplexed

with

addresses

from

the

Video

Subsystem.

Since

the

Z80B

has

only

16

address

lines

it

is

necessary

to

remap

the

upper

5

lines

into

7

addresses

to

achieve

a

full

18

address

lines

(thus

generating

a

"Global

Address").

A.

Address

Mapping

RAM

The

Microprocessor

MUX

located

at

U4

sends

the

Z80B

address

lines

A11-Al5

to

the

Mapping

RAM.

This

RAM,

consisting

of

four

74S189

memory

chips

(static),

is

arranged

in

pairs

so

that

each

chip

receives

all

five

address

lines.

Each

pair

of

RAM

chips

is

also

connected

to

the

CPU

Data

Bus

lines

DO

through

D7.

The

A1l5 line

is

inverted

so

that

it

can

be

used

to

chip-select

alternate

pairs

of

RAM.

Each

pair

of

RAM

chips

act

as

16

registers

giving

a

total

of

32

mapping

registers.

Each

of

these

registers

contains

a

7-bit

value

which

is

used

to

select

one

of

128

2

K

RAM

blocks

(See

Exhibit

II-4).

By

using

the

OUTP

r

command

any

of

the

values

in

these

registers

can

be

changed.

1i.e.

Changing

one

register

results

in

a

different

2

K

block

of

memory

being

addressed.

NOTE:

the

VECTOR

4

PROGRAMMERS

GUIDE

contains

more

detailed

information

on

how

the

OUTP

r

command

is

used

(See

Exhibit

II-5).

Once

the

Address

Mapping

RAM

registers

have

the

proper

value

they

can

be

used

for

typical

memory

READ

and

WRITE

operations.

In

this

case

address

lines

A11-A15

gecess

the

contents

of

the

registers

resulting

in

a

new

set

of

address

lines

A11-Al17

(See

Exhibit

II-6).

These

address

lines

are

combined

with

the

unmapped

A0-A1l0

lines

at

the

CPU/VIDEO

Address

MUX

(<B3>).

09-01-82

7200-0001

I

2-7