Vector 4 - Page 54

B.
VECTOR 4
TECHNICAL INFORMATION
PU/VIDEO MUX Contrg P PDEQ Address MUX
The CPU/VIDEO MUX Control subsystem generates two controls:
- Multiplexing the Video and CPU Subsystem addresses.
- Multiplexing the high and low order addresses out the Multiplexed
Address Bus.
Exbibit VI-5 showed how the Video and CPU cycles were interleaved through
the generation and use of the WAIT State. The signal which ultimately controls
this interleaving is the CPU/VID which is generated by the Clock Subsystem.
This signal (in both active high and active low forms) along with MHIGH| and
MHIGH provide the control lines for the CPU/VIDEO MUX Control Subsystem.
When CPU]/VID is LOW, CPU/VID| is HIGH. These signals can be deseribed as
logically active and inactive only when referring to the status of the
Multiplexed Address Bus. For example, when CPU|/VID is LOW and CPU/VID| is
HIGH the Multiplexed Address Bus is reserved for use by the CPU Subsystem.
However, if you look at page 2 of the SBC Schematic you will note that these
signals are used in other places. In particular, CPU|/VID is used to multiplex
8-bits of data from a latech to the Character Generators during the CPU Cycle
and not the VIDEO Cycle (This was explained in Exhibit VI-5). For this reason
it is especially important to observe the nature of these control signals in
relation to the overall operation of the SBC.
The four signals CPU|/VID, CPU/VID|, MHIGH| and MHIGH are generated
simultaneously by the Clock Subsystem. During the CPU cyecle this results in
the following sequence of data movements. CPU/VID signals will refer to use
of Multiplexed Address Bus.
1. CPU|/VID (active LOW) and MHIGH|(when HIGH) enable buffer U45 (from
the CPU/VIDEO Address MUX) which releases 7-bits (low order byte) of
data to the the Multiplexed Address Bus. This data is inturn received by
the Dynamic RAM where through the use of RAS and the Dynamic RAM
Decoder it provides 1/2 of a RAM address.
2. CPU|/VID and MHIGH (when HIGH) enable buffer U63 in the same manner
as buffer U45 was enabled except this time the high order byte is sent
out the Multiplexed Address Bus. This data is inturn received by the
Dynamiec RAM where through the use of CAS and the Dynamie RAM
Decoder it provides 1/2 of a RAM address.
Also during this time the T4LS367 (quadrant B-2 on page 1 of SBC
Schematie) is enabled by CPU|/VID *. This results in the generation of
the MA17 signal which is used by the Dynamic RAM Decoder.
* Not shown on this schematiec.
09-01-82 7200-0001 II 2-11