Vector 4 - Page 74

VECTOR 4
TECHNICAL INFORMATION
3.2 HOW THE SBC GENERATES
THE ALPHANUMERIC VIDEO DISPLAY
Summary: In the previous section the two display modes (Alpha and
Graphic) were described. This section will discuss the subsystems used
in the Alpha Video Mode. |
The VIDEO Cyele is initiated by the falling edge of the CPU/VID| signal. During
this edge a 16-bit value (multiplexed MAO-MAT lines) is sent from the CPU/VIDEO
Address MUX to the Multiplexed Address Bus. This address along with the RAS
signal (from Clock Subsystem), and CASx signal (generated by Dynamic RAM
Decoder) is used to index a 16-bit data value.
This 16-bit value is simultaneously clocked into both latches of the Video MUX
Latch Subsystem (See Exhibit II-10). During the VIDEO Cyele the US7 Latch is
enabled (No longer in a HI-Z state). Therefore the data in the U57 latch (Least
Significant Byte from J_fi__mt___f_e_tgh) is released and processed by the remainder of
the Video System. This processing (described in next paragraphs) requires the use
of LATCH, LATCH|, LATCH1| and other control signals (See Exhibit VI-3).
The rising edge of the CPU/VID| signal indicates the end of the VIDEO Cyecle and
the beginning of the CPU Cycle. During this time frame the U58 Latch is enabled
resulting in the Most Significant Byte being released to the remainder of the Video
System.
The 8-bit value coming from the Video MUX Latch Subsystem is divided into 7 and
1 bit components. The 7-bit component (bits 1-7) are routed to the Character
Generator PROMs. These PROMs are indexed by Lines L0-L3 (lines RA3-RA0 from
the Video Controller). At the end of the Cyecle the LATCH signal or "character
clock™ loads the Character Generator output (16-dot value) into the two Alpha Mode
Shift Registers.
The 1 bit component (8th bit of the each byte) is used to determine if the
character is displayed in reverse video (green character on a black background).
This 8th bit is sent from the VIDEO MUX Lateh to a 74S74 FF (U71) located
within the Video Combiner Subsystem.
The 16-dot value is shifted out of the Alpha Mode Shift Registers using the 32 M
signal generated by the Clock Subsystem. These bits go to the Alpha/Graphic MUX
where they are multiplexed with several signals. These signals are described below:
LATCHIIl Used in conjunction with DISPEN (from Video Controller) to disable
the Alpha mode scereen display during horizontal and vertical retrace
periods.
09-01-82 7200-0001 II 3-11