Vector 4 - Page 76

VECTOR 4
TECHNICAL INFORMATION
LATCHO! Used to load in data from the RAM to the Graphie Mode Shift
Registers. = However, in this application it is used in conjunction
with the DISPEN to disable the Graphies mode sereen display during
horizontal and vertical retrace periods.
Data (2A) Input line of dots from Alpha Mode Shift Registers.
Data (2B) Input line of dots from Graphiec Mode Shift Registers.
32M Clocking for Alpha Mode.
16M Clocking for High Resolution Graphies Mode.
After the 16-dot alpha value has been selected by the Alpha/Graphiec MUX it is
routed to a NOR gate where it is combined with the output from a FF (74S74)
(U71). This results in the correct signal (reverse or normal video) being routed
during the correct time slot.
The 16-dot value is then sent to a NAND gate where it is combined with a signal
(from U91) that determines if the video is going to be displayed. The resultant
signal
is
clocked
into
a
FF
(U91)
at
a
rate
determined
by
the
output
(4Y)
of
Alpha/Graphic MUX. The DIG/GRY]| signal will be HIGH thus allowing the bits to
be shifted out through pin 2 of a 6-pin molex connector (J13).
The video data is then routed to the contrast control POT on the front panel. The
H Sync and V Sync signals (from the 6545A-1) are routed out pins 5 and 4 (See
= in Section IV). These signals are combined with the power lines
(from the Switching Power Supply) and sent to the Video Board.
The Video Board (Described fully in Section IV) sends the 16-bits of data to the
CRT where it is displayed on the screen as gone scan line of one character cell.
The complete character cell consists of a matrix which is 16 1/2 dots wide by 13
dots high. Therefore the complete character cell requires 13 scan lines. These
scan lines are generated for each character cell by the sequencing of the L0-L3
lines coming from the RA Register of the Video Controller chip.
As was discussed in the beginning paragraphs of this section, the L0-L3 lines are
tied to the Character Generators. Hence, when the Video Controller increments
these lines the Character Generators address lines (pins 1, 22, 23, 19) get
incremented. This results in the Character Generators outputting another scan line
for a particular character cell, This procedure continues for 13 scan lines or until
the the Video Controllers RA Register has completed its binary count (0-121g). At
the end of this cycle a new row of character cells is sequenced in memory and the
scan line cycle for each character cell begins again.
Exhibit II-11 shows how the scan lines are generated. Part VI shows the complete
Character Sets for 60 Hz and 50 Hz systems (Exhibits VI-6, VI-T).
09-01-82 7200-0001 II 3-13