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Vector 4 - Page 80

Vector 4
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VECTOR
4
TECHNICAL
INFORMATION
3.3
HOW
THE
GRAPHIC
MODES
"WORK
Summary:
In
Section
3.1
the
various
screen
display
modes
were
defined.
This
section
will
describe
the
three
types
of
Graphic
Modes.
A‘-
Iio
]
B
A
]
Io
G
l
.
Exhibit
II-9
showed
that
the High
Resolution
Mode
allows
the
programmer
to
program
individual
bits.
This
results
in
each
scan
line
having
640
programmable
pixels.
This
mode
(and
all
Graphic
Modes)
require
a
26
K
block
of
memory.
The
beginning
address
of
this
block
can
be
changed
by
outputting
a
specific
value
to
register
13
of
the
Video
Controller
(Will
use
ports
OEH
and
OFH).
This
procedure
is
described
in
the
VECTOR
4
PROGRAMMERS
GUIDE.
The
High
Resolution
Mode
is
initiated
by
outputting
a
value
to
the
Subsystem
Port
Register.
This
procedure
is
also
used
for
all
the
various
screen
display
modes.
The
following
chart
(Exhibit
II-12)
shows
the
values
which
must
be
sent
to
port
02H
or
03H
to
enable
the
different
type
of
video
modes.
After
the
Subsystem
Port
Register
has
the
proper
value
its
lines
will
remain
in
that
specified
state
until
another
output
instruction
is
used
to
change
their
values.
The
values
from
the
Subsystem
Port
Register
are
used
throughout
the
Video
System.
In
particular
the
ALPH|/GRAPH
signal
goes
to
the
Video
MUX
(<C2>)
where
it
is
used
to
to
enable
the
U81
buffer.
|
This
buffer
uses
the
Video
Controllers
address
lines
A11-A13
and
the
RA
lines
L3-L0
(See
chart
in
Section
3.1-C).
The
output
of
this
buffer
along
with
the
other
address
lines
from
the
the
Video
Controller
are
used
to
form
input
signals
for
the
CPU/VIDEO
Address
MUX.
This
MUX
outputs
two
groups
of
8-bit
addresses
and
sends
them
via
the
Multiplexed
Address
Bus
to
the
Dynamic
RAM.
NOTE:
A1l6
is
used
to
generate
MA1l7
whieh
does
not
go
through
the
Multiplexed
Address
Bus.
See
Section
2.1
for
a
deseription
of
memory
addressing.
At
the
Dynamic
RAM
the
Dynamic
RAM
Decoder
selects
a
16-bit
block
of
data
and
sends
it
to
the
four
Graphic
Mode
Shift
Registers.
The
LS
and
MS
bytes
are
loaded
into
these
registers
by
use
of
LATCHO|
(Rising
Edge).
From
this
point
the
data
is
shifted
serially
out
of
the
registers
to
the
Alpha/Graphic
MUX.
The
control,
input
and
output
lines
on
this
chip
are
used
to
move
this
16-bit
data
string
to
the
remainder
of
the
Video
Combiner
circuit.
The
Video
Combiner
circuit
routes
these
dots
using
the
circuitry
that
was
described
in
Section
3.2.
09-01-82
7200-0001
|
I
3-17

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