A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
AMD N/C: 9, 10, 13, 14
AMD RY/BY#: 15
----------------
MICRON N/C: 9, 10, 15
MICRON Vpp: 13
Boot Configuration Latch
Active during power-on
Boot Configuration Pull-Up: 0 1 0 0 1 0 0 1 1 1 1 0 0 0 0 0
(see page 4-10)
0: internal arbitration
1: MSR(ip) = 0, interrupt prefix is 0x0000
0: reserved
0: memory controller is active after reset
1,0: 16-bit boot device
0: reserved
1,1: IMMR base is 0xfff0-0000
1,1: DBGC mode
0,0: DBPC mode
0,0: External bus division factor
Jim Belesiu
Jim Belesiu
Mar 5, 1999
Mar 5, 1999
620005.dsn
JAC5-39173 3/18/99
L. Phillips
Z. Psenicnik
J. Bello
3/19/99
3/19/99
3/19/99
LPP
B
ZIP4/15/99JJC5-39353Component change for
frequency modulation
Change Reset IC U3,
No Load C40
C 6/24/99LPP5-39830
REV
Description
ECN/ECO Init
Date Ckd
A Release to Production
620005
C
Flash, SDRAM and HRESET Config Word
C
46Thursday, June 24, 1999
Title
Size
Document Number
Rev
Date: Sheet of
Welch Allyn Inc.
Schematic:
Release For Production
Approved
Checked
Designed
Drawn
Initial Date
A20
A22
A26
D13
dx7
GPL1
A24
A17
A13
D6
D4
dx9
A28
A10 A9
D14
D15
dx1
dx8
dx11
GPL0
A21
A22
D6
D3
D1
A28
A12
D2
D0
D10
A27
CS_n1
D11
D10
D1
D11
dx10
D9
D9
D9
D4
D8
D8
A30
D8
D4
D10
A21
A19
A15
D2
dx12
A25
A25
A23
A14
A11
A24
D13
CS_n0
GPL3
GPL2
A16
D7
D0
D14
GPL1
A23
D15
A29
A27
A29
D7
D5
D3
BS_AB1
A18
A30
D1
D7
dx4
D5
D12
BS_AB0
A26
D12
CLKOUT
BS_AB[0:3]
D[0:31]
GPL[0:7]
CS_n[0:7]
SRESET_n
HRESET_n
A[6:31]
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
U6
FLASH-512Kx16
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
13
37
47
9
14
46
27
28
26
11
12
10
15
16
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
NC3
Vcc
Byte#
NC1
NC4
Gnd-a
Gnd-b
OE#
CE#
WE#
RESET#
NC2
RY/BY#
A18
TP54
1
TP55
1
TP53
1
U5
SDRAM-1Mx16
2
3
5
6
8
9
11
12
39
40
42
43
45
46
48
49
21
22
23
24
27
28
29
30
31
32
20
38
13
14
33
36
26
47
37
19
18
17
15
16
4
10
41
34
35
50
1
25
44
7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
VccQ3
VccQ2
DQML
NC1
DQMH
Vss1
VssQ4
NC2
BA
CS#
RAS#
WE#
CAS#
VssQ1
VssQ2
VssQ3
CKE
CLK
Vss2
Vcc1
Vcc2
VccQ4
VccQ1
R57
100K
1 2
T1
U4
74AHC244
2
4
6
8
11
13
15
17
1
19
18
16
14
12
9
7
5
3
20 10
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
VCC GND
T2
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