Table 4: SOM240_1 Signal Pins (cont'd)
Pin Number Signal Name Signal Description
C3 HPA00_CC_P HPIO clock-capable pin on bank 66
C4 HPA00_CC_N HPIO clock-capable pin on bank 66
C5 GND Ground
C6 HPA03_P HPIO on bank 66
C7 HPA03_N HPIO on bank 66
C8 GND Ground
C9 HPA08_P HPIO on bank 66
C10 HPA08_N HPIO on bank 66
C11 GND Ground
C12 HPA10_CC_P HPIO clock-capable pin on bank 66
C13 HPA10_CC_N HPIO clock-capable pin on bank 66
C14 GND Ground
C15 PS_POR_L PS power-on reset driven by the carrier card. When deasserted, the PS begins
the boot process
C16 PS_SRST_C2M_L PS system reset driven by the carrier card. When asserted, forces the PS to
enter the system reset sequence
C17 GND Ground
C18 HDA06 HDIO on bank 45
C19 HDA07 HDIO on bank 45
C20 HDA08_CC HDIO clock-capable pin on bank 45
C21 GND Ground
C22 HDA18 HDIO on bank 45
C23 HDA19 HDIO on bank 45
C24 HDA20 HDIO on bank 45
C25 GND Ground
C26 MIO24_I2C_SCK PS I2C clock output
C27 MIO25_I2C_SDA PS I2C serial data
C28 MIO12_FWUEN_C2M_L Firmware user enable indication
C29 GND Ground
C30 MIO29 PS MIO signal on bank 501. No connect on the SOM
C31 MIO30 PS MIO signal on bank 501. No connect on the SOM
C32 MIO31_SHUTDOWN PS MIO signal on bank 501. Optional use as PMU input. Optional PMU library
enabled input for hardware-initiated shutdown by the PMU.
C33 GND Ground
C34 MIO47 PS MIO signal on bank 501
C35 MIO48 PS MIO signal on bank 501
C36 MIO49 PS MIO signal on bank 501
C37 GND Ground
C38 MIO55 PS MIO signal on bank 502
C39 MIO56 PS MIO signal on bank 502
Chapter 2: Electrical Design Considerations
UG1091 (v1.0) April 20, 2021 www.xilinx.com
Carrier Card Design for Kria SOM 14
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