ZiLOG S3F8S19 - Page 22

UM026803-0816 19
S3F8S19 Development Kit
User Manual
Figure 21. S3F8S19 Development Board Schematic Diagram, #2 of 2
UART CONNECTION
UART CONFIGURATION:
S3F8S19 UART1 R41 R39 (DEFAULT)
Z8F6481 UART0 R40 R38
UART
PA
5_T
XD0
PA4_RXD
0
VCC_
T
Z_DBG
Z
_RST
Z_RST
Z_DBG
Z_RST
PD5_TXD1
X
OUT
XIN
X
OUT
X
I
N
PD4_RXD1
R
xD
S3_RXD1
PA4_
R
XD0
S
3_
T
XD1
PA5_TXD
0
PA6_
S
CL
P
C4_MOSI
P
C5_SCK0
PA
7_S
DA
PC2_SS-
VCC_5V
VCC_T
VCC_T
VCC_T
VCC_5v
S
3_TXD1
S
3_RXD1
S3_RXD0
S3_TXD0
S
3_
S
DA
S3_SCK
S3_MOSI
S
3_SC
L
S
3_
SS-
S3_MISO
R
3
8 100 ohm
R17
19.
6
K
R
18
10K
R41 0 oh
m
R14
470
Y3
24
.000MH
Z
R34
3.3K
D7
1N4448W
R19
10K
U3
MIC5318
GND
2
E
N
1
IN
3
AD
J
5
OUT
4
BYP
6
Cen
ter Pa
d
7
R
20
2
7
J
1
4
1
C12
0
.
01uF
C
13
4.7u
F
J
1
5
1
R21
2
7
L1
FERRIT
E BEAD
C11
0.01uF
R
39 100
ohm
C
14
0.1uF
J12
1
C
9
4
.7u
F
C15
12pF
P1
USB,
m
in
i
B
VBUS
1
DM
2
DP
3
ID
4
GN
D
5
SH1
6
SH2
7
S
H3
8
S
H4
9
h1
10
h2
11
R40 0 oh
m
J16
HDR/P
I
N 2
x
3
1
2
3
4
5
6
C16
12pF
C8
1uF
C
5
4.7uF
C
10
0.1u
F
R
35
4.7K
R
16
20
K
1
3
2
J11
1
D5
GREEN
2
1
C7
1uF
Z
8F6481AN
U4
PA2/DE0/
C
LK2I
N
/
X
2IN
1
PA3/CT
S0-
/X2O
UT
2
PE
3
/
T
4CHA/
ESOU
T0
3
PD6/
D
E1
4
PA4/RXD0/
MO
SI0
5
PA5/TXD
0/SCK0
6
P
D5/TXD1
7
PA
6
/
T
1IN/
T
1OUT-/
S
CL
8
PC4/
MO
SI0/T0IN/T0OUT-/SCL/
D
E0
9
P
C5/SCK0/T0OUT/
S
DA/CTS0-
10
PA
7
/
T
1OUT/
S
DA
1
1
PD4/
RXD1
12
PC6/T2IN/T2OUT-/SCKOUT/ESOUT0
13
P
C7/T2OUT/
CTS1-
/ESOUT1
14
VDD
15
PD0/
RESET-
16
D
BG
17
P
D3/C1OUT/AMPBOUT/
AN
A8
18
VSS
19
PC0/
AN
A4/VB
IAS/C
0INP
21
P
C1/MI
S
O0/ANA5/C0INN
2
2
PC2/
AN
A3/SS0-
23
PC3/MI
S
O0/ANA11
/DAC
24
PD2/
C1I
N
P/AMPBI
N
P/
A
NA6
2
5
P
D1/C1I
NN
/
AM
PB
INN/ANA
7
26
PB0
/
AN
A0/AMPAOUT
27
PB
1
/
A
NA1/AMPAINN
2
8
PB
2
/
A
NA2/AMPAINP
2
9
PB4/VR
EF+
30
PB3/VREF-
31
PE5/T4CHC/ESOUT2
32
PE6/T4
CHD
/ESOUT3
3
3
PE2/
T
4IN
34
VCORE
3
5
AVDD
3
6
V
DD
37
PA
0
/
T
0IN/T0OUT-/
C
LKI
N/XIN
38
PA
1
/
T
0OUT/
X
OUT
3
9
VSS
4
0
AVSS
41
PD7/
C
0OUT
42
PE1/
D
M/
T
0OUT
43
PE
0
/
DP/
T
0IN/T0OUT-
4
4
PE4/T4CHB/ESOUT1
2
0
J20
1
2
3
4
5
6
R
15
16.5K
R36
3
.
3
K
C
6
0.1uF
R
33 4.7K