ZiLOG Z8 - Page 197

Z8 Microcontrollers
ZiLOG Instruction Descriptions and Formats
UM001601-0803 12-57
RR
ROTATE RIGHT
RR
Rotate Right
RR dst
Instruction Format:
Operation:
C <— dst(0)
dst(0) <— dst(1)
dst(1) <— dst(2)
dst(2) <— dst(3)
dst(3) <— dst(4)
dst(4) <— dst(5)
dst(5) <— dst(6)
dst(6) <— dst(7)
dst(7) <— dst(0)
The contents of the destination operand are rotated to the right by one bit position. The initial value of bit 0 is moved
to bit 7 and also into the C Flag.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working
Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op Code.
Flags: C: Set if the bit rotated from the least significant bit position was 1 ( i.e., bit 0 was 1).
Z: Set if the result is zero; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred (if the sign of the destination operand changed during rotation);
cleared otherwise.
D: Unaffected
H: Unaffected