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COMMENTS
Invalid LINKS can be caused by solder shorts, PCB faults or internal IC faults and can be in
many configurations on numerous ICs. They may also be caused by novel or unexpected
ways of using an IC in a design, which the AUTOMATIC CIRCUIT COMPENSATION software is
incapable of resolving. They are difficult to identify as Links but the indication is valid when
the circumstances are understood. The tester informs you of what is seen when testing the
device. It has flagged a failure for the device and you must investigate the problem to find
the root cause.
EXERCISE 24 : TRI-STATE DEVICES
ACTION
Ensure BDO is removed. Attach SOIC Test Cable the BFL. Attach 20 way or more SOIC clip to
cable. Attach clip to U13 74LS244 and press STARTon the IC tester. Observe test result.
DESCRIPTION
In many designs, the TRI-STATE outputs of one IC will be connected to the outputs of
another IC in a bus-structured configuration. In normal operation, the logic on the board will
ensure that only one output at a time can be enabled. From studying the circuit you can see
that the tester can backdrive the Enable signal (Pins 1 & 19) to carry out a complete and
effective test on this device as the Address lines on the other device on the bus (U10) are not
enabled so there will be no output contention.
COMMENTS
The Preliminary and connections tests carried out by the tester identify if there will be a
problem from other devices on the same bus. By 'Disabling' the device under test the tester
will then monitor all the outputs for a logic condition. As the device is turned off, the outputs
should all be Open Circuit (high Impedance).
Note to illustrate this further the BDO (green) can be connected to TP1 to disable the IC. The
outputs are then Open Circuit.
If it is seen that there is activity on the outputs then the device will show CONFLICTS.
Conflicts do not necessarily mean a device failure. This is due to the coincidence of the logic
levels such that there will be no failure of an output if there is a Logic High present from
another device on the bus at the same time as an expected Logic High output from the
device under test.
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