376 Chapter9
Assembly Descriptions and Block Diagrams
IF Section
• Final processing of the detected 21.4 MHz IF signal before the video
signal is converted by the ADC for further digital processing by the
central processing unit (CPU).
❏ Video bandwidths from 30 Hz to 3 MHz are available in a 1, 3, 10
sequence.
❏ The ADC input MUX selects the positive-peak detector, or
bypasses the positive-peak detector, and selects the sample
detector. In sample mode, the video signal passes directly to the
ADC from the video bandwidth circuitry.
❏ The MUX can also select the processed video signal from an
assembly in the card cage.
• Mathematical offset of the digitized video signal for greater
reference-level resolution and analyzer calibration accuracy.
• Digital control of analyzer assemblies directly over the IO bus.
• Analog control of analyzer assemblies via the A7 analog interface
assembly.
• Nonvolatile RAM memory-storage of DLP software, analyzer
calibration data, and error correction data. Refer to Chapter 13 for
more information about analyzer calibration and error correction.
• Processing and integration of trace and text information for output
to the A2 display assembly. The digitized video signal is merged by
the CPU with other trace information. The trace information is then
combined with text information for input to the display drive
circuitry.
• Generation of the A2 display drive signals. The digital display input
is converted back into analog voltages by the A16 display
drive-circuitry and sent to the A2 assembly. The display signal is
also sent to MONITOR OUTPUT on the rear panel.
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