Pin Port Nome Pin Name Description
55 P8.3 (SEG36)
56 P8.4 (SEG35)
57 P8.5 (SEG34)
58 P8.6 (SEG33)
59 P8.7 (SEG32)
60 P7.0 (SEG31)
61 P7.1 (SEG30)
62 P7.2 (SEG29)
63 P7.3 (SEG28)
64 P7.4 (SEG27)
65 P7.5 (SEG26)
66 P7.6 (SEG25)
67 P7.7 (SEG24)
68 P6.0 (SEG23)
69 P6.1 (SEG22) RVS_SW 3-CD Tokyo Pigeon Changer
70 P6.2 (SEG21) FWD_SW 3-CD Tokyo Pigeon Changer
71 P6.3 (SEG20) OPCL_SW 3-CD Tokyo Pigeon Changer
72 P6.4 (SEG19) CN1_SW 3-CD Tokyo Pigeon Changer
73 P6.5 (SEG18) CN2_SW 3-CD Tokyo Pigeon Changer
74 P6.6 (SEG17) HOME_SW 3-CD Tokyo Pigeon Changer
75 P6.7 (SEG16) EXTRA_SW 3-CD Tokyo Pigeon Changer
76 P9.0 (SEG15) CMF 3-CD Tokyo Pigeon Changer
77 P9.1 (SEG14) DMR 3-CD Tokyo Pigeon Changer
78 P9.2 (SEG13) DMF 3-CD Tokyo Pigeon Changer
79 P9.3 (SEG12) DMR 3-CD Tokyo Pigeon Changer
80 SEG11
81 SEG10
82 SEG9
83 SEG8
84 SEG7
85 SEG6
86 SEG5
87 SEG4
88 SEG3
89 SEG2
90 SEG1
91 SEG0
92 COM3
93 COM2
94 COM1
95 COM0
96 VLC LCD Power
97 PD0
98 PD1
99 PD2
100 VDD VDD
7473
IC301 TMP-87EP26F PINS DESCRIPTION - CONTINUED
Pin No. Pin Name Type Description
Reset,Standby and Idle Status Interface
124 RESET# I Reset input.Once de-asserted,the Decoder starts the initialization process.
122 STNDBY# I Stand-by input. When asserted together with RESET#, all outputs and bidirectional
pins float, such that the Decoder is electrically disconnected from its surroundings.
All internal clocks are disabled,and the power consumption is minimized.
160 IDLE 3-S Idle, Init and Reset states indication output.
Host Interface
2 HWID I Determines the width of the host interface data bus.It is allowed to be changed only
during RESET,A low level (GNDP) Configures the Decoder to an 8-bit host data
interface, a high level (VDDP) to 16-bit width.
1 HORD I Determines the order of bytes on the host interface data bus in case of 16-bit width
(HWID at VDDP). It is allowed to be changed only during RESET. A low level (GNDP)
configures the Decoder to input/output the m.s. Byte on HD [ 15:8 ]; A high level
(VDDP) to input/output the m.s.byte on HD [ 7:0 ], Must be at GNDP if the houst
data bus is 8 bits.
4 HTYPE I Determines the protocol type for the 8 and 16 bits modes host interface.It is allowed
to be changed only during RESET.A low level (GNDP) configures the Decoder to
type A, a high level (VDDP) to type B.
17,18 HD[7],HD[6] 3-S For 16 bits mode,the 8 I.S. Data lines of host data bus. For 8 bits mode,only these
20,21 HD[5],HD[4] signals are defined as host data signals.
22,23 HD[3],HD[2]
24,25 HD[1],HD[0]
9,11 HD[11],HD[10] 3-S When HWID is connected to VDDP,these are data lines 11:8 of the 16-bit host
13,15 HD[9],HD[8] data bus.
5,6 HD[15],HD[14] 3-S When HWID is connected to VDDP,these are data lines 15:12 of the 16-bit host
7,8 HD[13],HD[12]
data bus. When HWID is connected to GNDP, these are the CD-DSPI
2
pins as explained in the CD-DSP pin description.
27,28 HA[3],HA[2] I Host address inputs,These input signals indicate the register accessed in every
29,30 HA[1],HA[0] cycle on the host interface.
32 HCS# I Host chip-select input.
31 HWR#-HR/W# I In host protocol Type A(HTYPE= GNDP):HR/W# This input determines the direction
of the host access.
In host protocol Type B (HTYPE=VDDP):HWR#.Host write input.
34 HRD#-HDS# I In host protocol Type A (HTYPE = GNDP): HDS#. Data strobe input (active low)
In host protocol Type B (HTYPE=VDDP):HRD#.Host read input.(active low.)
36 HRDY 3-S Host ready output. When this signal is tri-stated (i.e, is requires a pull-up resistor),
up to SysConfig.CodBurstLed bytes of code can be written to the Decoder with no
need to poll its condition in between. When HRDY is low during a host access,
the Decoder may still receive at least two additional bytes of code without corrupting
the data.
37 HIRQ# 3-S Interrupt request. This output signal requests an interrupt from the host controller,
if one of the events associated to interrupts occurs,and it is not masked-off. It is
de-asserted if the host responds to the interrupt by reading the interrupt status
register, or if the host disables the interrupt, or after RESET
Deassertion of the HIRQ# output has two modes: De-activated and then tri-stated
or directly to is a tri-state condition. The pin needs external pull-up resistor.
39 HACK# HACK# Host acknowledge output. In protocol A, the Decoder indicates that a read or write
cycle is completed by asserting this output.In protocol B, this signal is used by the
Decoder to indicate a wait state that may be used by fast hosts. In protocol B the
host may ignore the HACK# signal.
When this signal is deasserted it is de-activated and then tri-stated. This pin needs
an external pull-up resistor.
U16 ZR36732PQC PINS DESCRIPTION
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