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Akai PDP4225M - Page 57

Akai PDP4225M
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HDLTEK
HT48R06A-1/HT48C06
Pad Description
Pad Name I/O Options Description
PA0~PA7 I/O
Pull-high*
Wake-up
Bidirectional 8-bit input/output port. Each bit can be configured as wake-up
input by options. Software instructions determine the CMOS output or
Schmitt trigger input with a pull-high resistor (determined by pull-high op
tions).
PB0/BZ
PB1/BZ
PB2
I/O
Pull-high*
I/O or BZ/BZ
Bidirectional 3-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with a pull-high resistor (determined by
pull-high options).
The PBO and PB1 are pin-shared with the BZ and BZ, respectively. Once the
PBO and PB1 are selected as buzzer driving outputs, the output signals come
from an internal PFD generator (shared with a timer/event counter).
VSS
Negative power supply, ground
PC0/INT
PC1/TMR
I/O Pull-high*
Bidirectional I/O lines. Software instructions determine the CMOS output or
Schmitt trigger input with a pull-high resistor (determined by pull-high op
tions). The external interrupt and timer input are pin-shared with the PCO and
PC1, respectively. The external interrupt input is activated on a high to low
transition.
RES I
Schmitt trigger reset input. Active low
VDD
Positive power supply
OSC1
OSC2
I
O
Crystal
or RC
OSC1, OSC2 are connected to an RC network or Crystal (determined by op
tions) for the internal system clock. In the case of RC operation, OSC2 is the
output terminal for 1/4 system clock.
* All pull-high resistors are controlled by an option bit.
Absolute Maximum Ratings
Supply Voltage
..............................
V s s - 0 .3 V to V s s + 6 .0 V Storage Temperature
................................
-50°C to 125°C
Input Voltage
..................................Vss- 0.3V to Vdd+0.3V Operating Temperature...............................-4 0 oC to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil
ity.
53/73

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