Alpine PKG-1000 - Page 19

Descri
p
tion of IC Terminal
(
BIT1675
)
Pin # Pin Nam
e
I/O Buffer T
yp
e Descri
p
tion
1 TEST
_
N I Pull U
p
Test
p
in : Normall
y
o
p
en or
p
ulled-u
p
2 IOAS I Pull U
p
I2C Slave address settin
g
(
L :1000100x, H : 1000101x
)
5-8 GPIO[9:0] I/O Pull U
p
General
p
ur
p
ose
p
ort : Re
g
ister IO mode, Status out
p
ut, et
c
10-13
16-17
18 IRQ
_
NOO
p
en Drai
n
Interru
p
t re
q
ues
t
20 SCL I --
-
I2C Bus cloc
k
21 SDA I/O O
p
en Drai
n
I2C Bus dat
a
22-23 SVO[9:0] O Tri State SV
p
ort - Video ou
t
25-28 For details,
p
lease refer to "
0
31-34 Video Port Inferface " on
p
a
g
e 4
5
36 SFLD O Tri State SV
p
ort - Field dis
p
la
y
37 SCBF O Tri State SV
p
ort - Cb dis
p
la
y
38 SVB O Tri State SV
p
ort - Vertical blankin
g
si
g
n
a
39 SHB O Tri State SV
p
ort - Horizontal blankin
g
si
g
n
a
40 SVS O Tri State SV
p
ort - Vertical s
y
nc si
g
n
a
41 SHS O Tri State SV
p
ort - Horizontal s
y
nc si
g
nal / CSYN
C
43-46 DVO[15:00
}
O Tri State DV
p
ort - Video ou
t
51-52 For details,
p
lease refer to "
0
54-55
57-60 Video Port Interface" on
p
a
g
e 45
63-66
49 SC
K
O--
-
SV
p
ort - Cloc
k
67 DTRDY I Pull U
p
DV
p
ort - Tar
g
et read
y
si
g
na
l
69 DC
K
I/O --
-
DV
p
ort -Cloc
k
71 DVA
L
O Tri State DV
p
ort - Data enable / Gated cloc
k
72 DGHP O Tri State DV
p
ort - Horizontal
g
eneral
p
ur
p
ose si
g
n
a
73 DGVP O Tri State DV
p
ort - Vertical
g
eneral
p
ur
p
ose si
g
n
a
74 DGP0 O Tri State DV
p
ort - General
p
ur
p
ose si
g
nal
0
75 DGP1 O Tri State DV
p
ort - General
p
ur
p
ose si
g
nal
1
77 CKX2 O --
-
Clock out
p
ut
(
double the
p
ixel clock fre
q
uenc
y
79 CKX1 O --
-
Clock out
p
ut
(p
ixel clock fre
q
uenc
y)
81 XTLO O --
-
Cr
y
stal out
p
u
t
82 XTLI I --
-
Cr
y
stal in
p
u
t
84 VCX
O
O Tri State PWM out
p
ut for VCXO control volta
ge
86 PWDN I --
-
Power down :
When "H" is a
pp
lied,
p
ower down mode
(
releasable b
y
re
g
ister settin
g)
When "L" is a
pp
lied, nomal mod
e
87 TSCE
_
N I Pull U
p
Test
p
in : Normall
y
o
p
en or
p
ulled-u
p
89 OE I --
-
Out
p
ut
p
ort enable
:
When "H" is a
pp
lied, out
p
ut
p
orts
(
SVD, DVO
)
are enable
d
(
Onl
y
the used
p
ins will be enabled. For exam
p
le, when in S
V
p
ort 8-bit out
p
ut mode, unused lower 2 bits will be "Hi-Z
"
When "L" is a
pp
lied, the SVO and DVO
p
orts will be force
d
to "Hi-Z
"
90 RST
_
N I Pull U
p
Reset si
g
nal. Reset b
y
"L" in
p
u
t
91 TDO O Tri State JTAG
93 TDI I Pull U
p
JTAG
94 TMS I Pull U
p
JTAG
95 TC
K
I Pull U
p
JTAG
96 TRST
_
N I Pull U
p
JTAG
97 TAFE_N I Pull Up VAFE test pin : Normally open or pulled-up
102 AIN23 I Analog Analog video input, CH2 - 3(SV-C/D1-Pb/D1-Pr)
104 AIN22 I Analog Analog video input, CH2 - 2(SV-C/D1-Pb/D1-Pr)
106 AIN21 I Analog Analog video input, CH2 - 1(SV-C/D1-Pb/D1-Pr)
107 VBYP I Analog Analog chroma - Clamp voltage-in: usually connected with VCM
108 AIN20 I Analog Analog video input, CH2 - 0(SV-C/D1-Pb/D1-Pr)
110 AIN13 I Analog Analog video input, CH1 - 3(SV-C/D1-Pb/D1-Pr)
112 AIN12 I Analog Analog video input, CH1 - 2(SV-C/D1-Pb/D1-Pr)
113 VBYN I Analog Analog chroma - Clamp voltage-input: usually connected with VCM
114 AIN11 I Analog Analog video input, CH1 - 1(SV-C/D1-Pb/D1-Pr)
115 IBIAS I Analog Analog test pin: Usually connected with analog GND
116 AIN10 I Analog Analog video input, CH1 - 0(SV-C/D1-Pb/D1-Pr)
118 AIN00 I Analo
g
Analo
g
video in
p
ut, CH0 - 0
(
CVBS/SV-Y/D1-Y
120 AIN01 I Analo
g
Analo
g
video in
p
ut, CH0 - 1
(
CVBS/SV-Y/D1-Y
121 VC
M
O Analo
g
Analo
g
common volta
ge
122 AIN02 I Analo
g
Analo
g
video in
p
ut, CH0 - 2
(
CVBS-SV-Y/D1-Y
123 VB
G
O Analo
g
Analo
g
band-
g
a
p
volta
ge
124 AIN03 I Analo
g
Analo
g
video in
p
utm CH0 - 3
(
CVBS/SV-Y/D1-Y
126 VREF
N
O Analo
g
Analo
g
reference volta
g
e
(
ne
g
ativ
e