ASROCK B85M-ITX - Page 65

B85M-ITX
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Congure IO latency for channel A.
IO-L (CHB)
Congure IO latency for channel B.
ODT WR (CHA)
Congure the memory on die termination resistors' WR for channel A.
ODT WR (CHB)
Congure the memory on die termination resistors' WR for channel B.
ODT NOM (CHA)
Use this to change ODT (CHA) Auto/Manual settings. e default is [Auto].
ODT NOM (CHB)
Use this to change ODT (CHB) Auto/Manual settings. e default is [Auto].
Command Tri State
Enable for DRAM power saving.
MRC Fast Boot
Enable Memory Fast Boot to skip DRAM memory training for booting faster.
FIVR Conguration
FIVR Switch Frequency Signature
Select whether to boost or lower the FIVR Switch Frequency.
FIVR Switch Frequency Oset
Congure the percentage of frequency boost or deduction.
CPU Override Voltage
Congure the voltage added to the CPU when the system is under heavy load.
CPU Voltage Oset
Congure the dynamic CPU voltage added to the CPU.