ASROCK H570M-ITX/ac - Page 65

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H570M-IT X/ac
tRDWR_dr
Congure between module read to write delay.
tRDWR_dd
Congure between module read to write delay.
tWRRD_sg
Congure between module write to read delay.
tWRRD_dg
Congure between module write to read delay.
tWRRD_dr
Congure between module write to read delay.
tWRRD_dd
Congure between module write to read delay.
tWRWR_sg
Congure between module write to write delay.
tWRWR_dg
Congure between module write to write delay.
tWRWR_dr
Congure between module write to write delay.
tWRWR_dd
Congure between module write to write delay.
Round Trip Timing
Round Trip Timing Optimization
Auto is enabled in general case.
Rx FiF0 Delay Oset
Congure Rx FIF0 Delay Oset.
Initial RTL (A1 Rank1)
Congure round trip latency initial value.