ASROCK Z690 PG Riptide - Page 80

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Z690 PG Riptide
ODT PARK (A1)
Congure the memory on die termination resistors' PARK for channel A1.
ODT PARK (A2)
Congure the memory on die termination resistors' PARK for channel A2.
ODT PARK (B1)
Congure the memory on die termination resistors' PARK for channel B1.
ODT PARK (B2)
Congure the memory on die termination resistors' PARK for channel B2.
Advanced Setting
ASRock Timing Optimization
Congure the fast path through the MRC.
ASRock Second Timing Optimization
Congure the second fast path through the MRC.
Realtime Memory Timing
Congure the realtime memory timings.
[Enabled] e system will allow performing realtime memory timing changes aer
MRC_DONE.
Early Command Training
Congure the Early Command Training.
Early Command Training is the initial step aer reading SPD and conguring DDR
interface to desired speed/timings.
Read Equalization Training
Congure the Read Equalization Training.
Reset for MRC Failed
Reset system aer MRC training is failed.
MRC Training on Warm Boot
When enabled, memory training will be executed when warm boot.