Asus A6J - Page 48

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1. Page2: Add test points T215 and T216 for H_ADS# and H_CPURST#
R1.0 -> R1.1
2. Page4: Modify FAN solution from DA to PWM and change R-C delay timing.
5. Page5: Add (R579*33 ohm and C529*10pF) for TPM PCI 33MHz clock
4. Page4: Add pull-down resister R418*10M ohm to protect noise when power-on
A. Mount R416 and DNI R415
B. Change C404 to 1uF
3. Page4: Connect +3VS_FAN(R419*3.3K ohm and R420*2.2K ohm from +V5S_FAN) to U401.3
分壓
because FAN_DA level is 3V and FAN_PWM# is open-drain, change pull-up to +3VS and U401.3
level shift from 5V to 3V
6. Page5: Change R531 from 10 ohm to 22ohm to eliminate swing.
7. Page5: DNI R510 to disable ITP enable.
8. Page7: Delete R715 because it duplicate with R529.
9. Page9: Change L905 to P/N:09G012030000 and L905 to P/N:09G013120409 because +1.5VS_PCIE
consume about 1.3A and +1.5VS_3GPLL consume 200mA only.
10. Page13: VGA_GPIO5 add pull-up 10K ohm to +3VS for ATI recommendation.
12. Page13: Add R1343*0 ohm for reserving bead to ground.
11. Page13: DNI R1320 and mount R1321 to change back light enable from DC level to PWM and
meet VBIOS support.
13. Page15: Change L1504.2 to connect from +VGA_VCORE to +1.2VSP for ATI recommendation.
14. Page15: Change bead L1506 from 120Ohm/100Mhz to 30Ohm/100Mhz type.
15. Page19: Add bead L1913 between TV_GND and GND.
16. Page23: Change High Definition damping resisters*R2312, R2314, R2316, R2318, R2320,
R2322, R2324, R2325 from 22 ohm to 39 ohm for reducing reflection.
17. Page29: Add Line-in solution, please commt Black 2.
18. Page31, 32: Change LAN chip from Marvell 88E8053 to Realtek RTL8111B.
19. Page34: Add Q3401 and R3414 to replace U3402B.
20. Page34,35: Modify reset circuits to meet Intel specification, please commt Black 3.
21. Page35,43 : DNI R4312 and change R3509 from 4.7M ohm to 2.2 M ohm to short SWDJ_EN#
detected to 2secends for BIOS requirement and add INIT# solution(please comment Block 7).
22. Page37: Change R3706 from 10K ohm to 100K ohm to enlarge R-C delay time.
23. Page39: Reserve R3905 to PLT_RSTNS# Wire-Or with PLT_RST#_BUF.
24. Page41: Short CON4101.1 and CON4101.2 and delete R4105, R4104, and C4103 because no
timing issue between power and enable signal.
25. Page42: Delete D4201 and DNI R4202 because no power loss issue exist.
26. Page43: Modify S4 strech circuits, please comment Block 4.
27. Page44: Add TPM connecter.
28. Page45: Add C4508, C4509, R4506 and R4507 for EMI requirment.
29. Page42: Change CON4202.1 and CON4202.3 power from +3VSUS to +3V.
30. Page18: Change L1806.2 power from AC_BAT_SYS to AC_BAT_SYS_CPU for EMI requirement.
31. Page7: Change from VRM_PWRGD to ICH7_PWROK to enable MCH_PWROK for Intel
requirement(Mount R721 and DNI R722).
32. Page23,34: Change thermal-trip solution.
A. Mount R2315 and DNI R4507
B. Remove the circuits.(please comment Block 5)
C. Mount thermal protection circuits.(please comment Block 6)
33. Page5, 23, 37: Change capacitor values for TXC recommendations(C513,C514 from 33pF to
27pF, C2302, C2304 from 12pF to 22pF ,Change X3701 to 07G010S22450*30 ppm and C3725 and
C3726 to 22pf).
34. Page15, 47: Add Back Bias circuits for ATI recommendations.
35. Page5, 23, 33: Add SATA circuits for OEM requirement.
36. Page12: Remove R1205 for ATI recommendations.
37. Page39: Reserve R-C to tune waveform quanlity.(R3906,R3907,C3911,C3912)
38. Page41: Reserve R4104, R4105, R4106 to modify enable blue tooth solution.
R1.1 -> R2.0
1. Page4, 34: Add power limit solution and change thermal protection solution.
A. Add R421*0 ohm and connect to H_PROCHOT_S#
B. DNI R417*0 ohm
C. Add R422*0 ohm and connect to OVERTEMP# that is wire-or with FORCE_OFF#.
D. DNI OTP solution.
2. Page15: Add BBIAS_CNTL pull-down resister R1508*10K ohm to GND.
3. Page19: Modify parts (D1912 and F1901).
4. Page24: Add 3 pcs decoupling CAPs(C2410, C2411, C2412) to short return path because PCI
Bus(IN1) reference +1.8VS(Vcc).
5. Page25, 44: Add BT_LED solution to co-layout with Scroll Lock for Epson requirement.
6. Page27: Change R2704 from 0 ohm to 150 ohm.
10. Page31: Change LAN chip reset signal from PLT_RSTNS# to PCI_RST#. (Mount R3107 and DNI
R3106).
9. Page30: Add LID switch solution.
7. Page27: Change R2707 from 47K ohm to 332K ohm.
8. Page27, 28: Add MUTE_POP# solution for Epson requirements. Please comment PR BlOCK 1.
A. Change BAT_SEL# push-pull resister from +3V to GND.
B. DNI Q3002*2N7002.
11. Page35: Change KBCRSM solution to connect to PM_PWRBTN# directly, please comment PR
BLOCK 2.
13. Page39: Add WLAN_LED# pull-high resister R3908*100K ohm to solve LED was lighted when
miniCARD was un-plug in.
12. Page36: Change CARDBUS chip reset signal from PLT_RST#_BUF to PLT_RST#. (Mount R3618
and DNI R3617).
Custom
48 63Tuesday, November 22, 2005
ASUSTeK COMPUTER INC
History (1)
2.0
A6J
Marco Chen
<Variant Name>
Size Project Name
Rev
Date: Sheet of
Title :
Engineer: