Asus ROG STRIX Z490-H GAMING - Page 23

ROG STRIX Z490-H GAMING BIOS Manual
23
IO Latency offset
CHA IO_Latency_offset
Configuration options: [Auto] [0] - [127]
CHB IO_Latency_offset
Configuration options: [Auto] [0] - [127]
IO Latency RFR delay
CHA RFR delay
Configuration options: [Auto] [0] - [127]
CHB RFR delay
Configuration options: [Auto] [0] - [127]
Memory Training Algorithms
The items in this menu allows you to enable or disable different Memory Training
Algorithms.
Early Command Training
Configuration options: [Enabled] [Disabled]
SenseAmp Offset Training
Configuration options: [Enabled] [Disabled]
Early ReadMPR Timing Centering 2D
Configuration options: [Enabled] [Disabled]
Read MPR Training
Configuration options: [Enabled] [Disabled]
Receive Enable Training
Configuration options: [Enabled] [Disabled]
Jedec Write Leveling
Configuration options: [Enabled] [Disabled]
LPDDR4 Write DQ DQS Retraining
Configuration options: [Enabled] [Disabled]
Early Write Timing Centering 2D
Configuration options: [Enabled] [Disabled]
Early Read Timing Centering 2D
Configuration options: [Auto] [Enabled] [Disabled]
Write Timing Centering 1D
Configuration options: [Enabled] [Disabled]
Write Voltage Centering 1D
Configuration options: [Enabled] [Disabled]
Read Timing Centering 1D
Configuration options: [Enabled] [Disabled]
Dimm ODT Training*
Configuration options: [Auto] [Enabled] [Disabled]