86 APx PDM I/O Module for B Series: Specifications
PDM
Clock Jitter (Advanced Master Clock required)
Jitter Measurement
Range 0 to 650 ns
Detection Peak, RMS or Average
Bandwidth
Low Limit 50 Hz or 700 Hz
High Limit Variable in 0.1 kHz steps,
Butterworth or Elliptic response
1 kHz 150 kHz
Accuracy (1 kHz)
“Average” detection ±(1% + 300 ps)
Flatness
1
100 Hz to 100 kHz ±0.2 dB
Residual Jitter
1
700 Hz to 100 kHz BW 600 ps
Jitter Spectrum
1
Spurious products
are typically
–40 dBc (below jitter
signal) or
–60 dBUI,
whichever is larger.
2
PDM Input Jitter Tolerance
Sine wave jitter, bit clock rates
from 128kHz to 24.576 MHz.
3.5 UI,
(subject to
1591 ns max
jitter limit)
Induced Jitter
Waveforms Sine, Square, Noise
Signals Affected Bit Clk and Data
Parameter Symbol Test Conditions Min Typ Max Unit
To Next Page
Loading...
Need help?
General
