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Overview of the on-chip processor and memory system architecture.
Key features of the BL602/BL604 system, including processor and memory.
Describes the bus connection, masters, slaves, and address access.
Lists the available interrupt sources and their corresponding numbers.
Introduces chip reset sources and clock sources for the system.
Details the different hardware and software reset sources available.
Describes the available clock sources and their distribution.
Introduces the Global Register module for chip settings.
Explains GLB functions: clock, reset, bus, memory, and GPIO management.
Lists and describes registers related to clock configuration.
Overview of the 12-bit successive approximation ADC.
Highlights ADC performance, resolution, modes, and channels.
Details the ADC's block diagram and operational parts.
Lists and describes ADC configuration and status registers.
Introduces the built-in 10-bit DAC with 2 modulation outputs.
Lists DAC features like accuracy, clock selection, and DMA support.
Describes the DAC module's block diagram and operation.
Lists and describes DAC configuration and DMA registers.
Explains DMA as a memory access technology for efficient data transfer.
Lists DMA features like channels, access width, triggers, and peripherals.
Details DMA transactions, channel configuration, and peripheral support.
Describes memory-to-memory, memory-to-peripheral, and peripheral-to-memory modes.
Lists and describes DMA control and status registers.
Describes the L1 Cache Controller for managing buffers and speeding up Flash access.
Highlights L1C features like mapping, cache size, and performance statistics.
Explains mutual conversion between TCM and Cache RAM resources.
Lists and describes L1C configuration and counter registers.
Introduces infrared remote technology and its components.
Lists IR features like protocols, waveform editing, and data handling.
Details IR protocols (NEC, RC-5) and pulse width reception/transmission.
Lists and describes IR transmit and receive registers.
Describes SPI as a synchronous serial communication interface.
Lists SPI features like master/slave modes, clock formats, and DMA support.
Explains clock control, master transmission, and acceptance filtering.
Lists and describes SPI configuration and interrupt registers.
Introduces UART as an asynchronous transceiver for full-duplex data exchange.
Lists UART features like data bits, parity, flow control, and DMA.
Details data format, clock source, baud rate, and flow control.
Lists and describes UART configuration and interrupt registers.
Describes I2C as a serial communication bus with multi-master-slave architecture.
Lists I2C features like host mode, arbitration, and clock frequency.
Explains start/stop conditions, data transmission, and arbitration.
Describes how the I2C clock is derived and divided.
Details configuration items like slave address, data length, and enable signals.
Explains I2C FIFO depth, status, and management.
Describes how to use DMA for I2C data transmission and reception.
Lists the different types of I2C interrupts.
Lists and describes I2C configuration and status registers.
Introduces PWM as an analog control method for modulating transistor bias.
Lists PWM features like channel generation and clock sources.
Explains clock and divider, and pulse generation principle.
Lists and describes PWM configuration and interrupt registers.
Introduces the 32-bit counters and watchdog timer.
Lists timer features like clock sources, dividers, and modes.
Details 8-bit divider, general timer mode, and watchdog timer mode.
Lists and describes timer and watchdog registers.
General| Brand | Bouffalo Lab |
|---|---|
| Model | BL602 |
| Category | Medical Equipment |
| Language | English |
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