Casio SF-8500 User Manual

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7) Power supply chip SC371015FU
VDD1
VDD2
VO1
VDD
PDB
GATE ARRAY
VOT terminal
FROM
(4.3 V ~ 4.7 V)
20 17
+
GND1
31
VSS(VREG) -3.07 -5.27
V1 +3.50 +3.23
V2 +2.57 +2.02
V3 -1.16 -2.80
V4 -2.11 -4.04
LCD DRIVE VOLTAGE Value (Approx.) [V]
Contrust : Min. Contrust : Max.
1
19
The IC SC371015FU is power supply chip for
SF-8500. When IC SC371015FU receives a Volt-
age 5V from main power supply circuit at the ter-
minal VDD1(Pin No.2), the regulated voltage
VDD (4.3~4.7V) will be applied to the VDD lines.
The outputs VSS (VREG) and V1~V4 are the
LCD drive voltages. When the terminal PDB be-
comes "H", those voltages are generated by IC
SC371015FU and capacitors C3 and applied to
LCD driver IC MSM6385AV-Z-358B.
The voltages for LCD driving are shown below:
MAIN POWER
SUPPLY CIRCUIT
GND2
SUB IN
CR2032
Back-up battery
8
VSS
9
V1
V2
10
V3
11
V4
12
POWER SUPPLY CHIP
SC371015FU
6
5
4
V COMP2
V COMP1
V COMP0
SUB OUT
7
22
2
32
The V comp0 ~ V comp2 and Sub out outputs are the battery voltage detection outputs. According to
VDD1 and VDD2 voltages, those outputs will change the status as follows:
OUTPUTS STATUS "H" STATUS "L" NOTE
V COMP 0 When the VDD1,2 voltages When the VDD1,2 voltages Switch off the LCD
are more than 3.7±0.1V. are less than 3.7±0.1V. driving voltages
V COMP 1 When the VDD1,2 voltages When the VDD1,2 voltages Main battery check
are more than 4.38±0.155V.are less than 4.38±0.155V.
V COMP 2 When the VDD1,2 voltages When the VDD1,2 voltages Main battery check
are more than 4.58±0.165V.are less than 4.58±0.165V.
SUB OUT When the SUB IN voltage When the SUB IN voltage Back-up battery check
is more than 2.5±0.065V. is less than 2.5±0.065V.
3
C3

Casio SF-8500 Specifications

General

Brand	Casio
Model	SF-8500
Category	eBook Reader
Language	English