Cirrus Logic CDB4272 - Page 3

CDB4272
3
LIST OF FIGURES
Figure 1. Instrumentation Amplifier Configuration........................................................................... 6
Figure 2. Main Window ................................................................................................................. 13
Figure 3. Advanced Window ......................................................................................................... 14
Figure 4. I²C Error Message.......................................................................................................... 14
Figure 5. Clock and Data Routing................................................................................................. 15
Figure 6. Hierarchy, Schematic Sheet 1 ....................................................................................... 16
Figure 7. CS4272, Schematic Sheet 2.......................................................................................... 17
Figure 8. Analog Input, Schematic Sheet 3................................................................................... 18
Figure 9. Analog Output, Schematic Sheet 4................................................................................ 19
Figure 10. CS8416 S/PDIF Receiver, Schematic Sheet 5............................................................ 20
Figure 11. CS8406 S/PDIF Transmitter, Schematic Sheet 6........................................................ 21
Figure 12. Board Setup, Schematic Sheet 7................................................................................. 22
Figure 13. PCM Header, Schematic Sheet 8................................................................................ 23
Figure 14. Control Port, Schematic Sheet 9.................................................................................. 24
Figure 15. Power, Schematic Sheet 10......................................................................................... 25
Figure 16 . Component Placement and Reference Designators.................................................. 26
Figure 17 . Top Layer................................................................................................................... 27
Figure 18 . Bottom Layer.............................................................................................................. 28
Figure 19 . Complete Analog Input Buffer Schematic.................................................................. 29
LIST OF TABLES
Table 1. System Connections......................................................................................................... 9
Table 2. Jumper/Switch Settings................................................................................................... 10