CDB4272
7
dielectric absorption properties. The HPF formed by this R-C pair must be such that the volt-
age across the aluminum electrolytic DC-block capacitor is minimal at 20 Hz. This keeps the
distortion due to the electrolytic's dielectric absorption properties to a minimum. For a design
utilizing only LPF configuration 1, there is no post-LPF resistor-divider pad, and a much
smaller value capacitor can be used (22 µF).
Similar to the output DC-block capacitor described above, the value of the AC coupling
capacitor from the non-inverting input of the 2-pole low pass to ground (C23 for AOUTR) was
also chosen to minimize the rise in distortion performance at low frequency due to the elec-
trolytic's dielectric absorption properties. These properties become apparent only as the
signal level on that leg increases to the levels output from the differential amp used in LPF
configuration 2. For a design utilizing only LPF configuration 1, the levels on that leg are suf-
ficiently low, and a much smaller value capacitor can be used (22 µF).
1.7 Stand-Alone Control
Switch S1 allows stand-alone hardware signal routing and configuration of the CDB4272.
See Table 2 for a list of the various options available. After changing settings using S1, the
user must assert a reset by pressing the RESET button (S2).
Operation in stand-alone mode requires the parallel port cable to remain disconnected from
the DB-25 connector (J31). Connecting a cable to the connector will enable the PC control
port, automatically disabling switch S1 and its associated logic.
1.8 PC Parallel Port Control
A graphical user interface is included with the CDB4272 to allow easy manipulation of all reg-
isters of the CS4272 and hardware configuration of the CDB4272. Connecting a cable to the
DB-25 connector (J31) will enable the PC control port, automatically disabling switch S1 and
its associated logic.
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