Conexant Fusion 878A - User Manual

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Summary

Product Overview

Detailed Features

Video Capture

Describes the Fusion 878A's integration of decoder, scaler, DMA, and PCI master for video capture and display.

Video DMA Channels

Explains separate destinations for odd/even fields, instruction lists, and pixel transfer.

Audio DMA Channels

Covers 8/16-bit digital audio samples, RISC program control, and independent operation.

UltraLock

Explains the proprietary technique for locking onto analog video signals.

Scaling and Cropping

Covers reducing video image size and arbitrary cropping of active scan lines/pixels.

Functional Description

UltraLock Functionality

Details the challenge of line length variation and UltraLock's solution.

Y;C Separation and Chroma Demodulation

Explains filters for separating Y/C signals and chroma decoding.

Video Scaling, Cropping, and Temporal Decimation

Details mechanisms to reduce video pixel data: down-scaling, cropping, temporal decimation.

Scaling Registers

Explains programming the Horizontal Scaling Ratio Register (HSCALE).

Vertical Scaling Ratio Register (VSCALE)

Details programming the VSCALE register for vertical scaling ratio.

Cropping Registers

Explains HDELAY and HACTIVE registers for defining active video region.

Temporal Decimation

Discusses temporal decimation register (TDEC) for skipping frames or fields.

Video Adjustments

Covers programmable hue, contrast, saturation, and brightness controls.

VBI Frame Output Mode

Explains VBI data capture in the active video region for still image capture.

Video Data Format Conversion

Details the conversion of video data from packed 4:2:2 YCrCb to other formats.

YCrCb to RGB Conversion

Details the conversion of 4:2:2 YCrCb data to 4:4:4 YCrCb before RGB conversion.

YCrCb Sub-sampling

Describes horizontal sub-sampling of 4:2:2 data to 4:1:1 and vertical sub-sampling.

Video and Control Data FIFO

Explains how the FIFO block accepts, buffers, and outputs data to the DMA controller.

FIFO Data Interface

Covers FIFO data loading, status codes, and interaction with DMA controller.

DMA Controller

Describes the DMA controller architecture for data delivery to memory.

Target Memory

Explains FIFO DWORD alignment to PCI bus and contiguous memory requirements.

RISC Program Setup and Synchronization

Details independent RISC instruction sets for odd/even fields and synchronization.

RISC Instructions

Lists five types of packed mode RISC instructions for FIFO data control.

Complex Clipping

Explains clipping video image for applications requiring occlusion by graphics objects.

FIFO Overrun Conditions

Covers cases where the PCI initiator cannot gain bus control, leading to FIFO overruns.

FIFO Data Stream Resynchronization

Explains how the DMA controller monitors and corrects mismatches in data streams.

Byte Alignment

Details byte alignment for target addresses in packed color modes.

Multifunction Arbiter

Explains the internal arbiter for determining PCI bus access between video and audio DMA.

Audio A;D

Covers multiplexing, anti-aliasing filtering, and input gain control for audio.

Input Gain Control

Digital Audio Packetizer

Audio Packets and Data Capture

Digital Audio Input Mode

Audio Dropout Detection

Electrical Interfaces

Input Interface

Crystal Inputs and Clock Generation

PCI Bus Interface

Covers the architectural, timing, electrical, and physical interface to the host CPU.

General Purpose I;O Port

SPI Input Mode

Digital Video Input Mode

I²C Interface

Details the two-wire serial interface for SCL and SDA data transfer.

I²C Serial EEPROM Interface

Subsystem Vendor ID

Power Management Interface

Discusses power management states D0, D3hot, and D3cold support.

D3 Power States

JTAG Interface

JTAG Approach to Testability

Verification with the TAP Controller

Control Register Definitions-Function 0

Device Status Register (DSTATUS)

Holds status bits for video presence, H-lock, field, line count, and ADC overflows.

Input Format Register (IFORM)

Temporal Decimation Register (TDEC)

Horizontal Scaling Register, Upper Byte

Horizontal Scaling Register, Lower Byte

Brightness Control Register (BRIGHT)

Miscellaneous Control Register

Luma Gain Register, Lower Byte (CONTRAST_LO)

Chroma (U) Gain Register, Lower Byte (SAT_U_LO)

Chroma (V) Gain Register, Lower Byte (SAT_V_LO)

Hue Control Register (HUE)

SC Loop Control Register

Vertical Scaling Register, Upper Byte

Vertical Scaling Register, Lower Byte

Software Reset Register (SRESET)

Color Format Register (COLOR_FMT)

Color Control Register (COLOR_CTL)

Integer Register (PLL-XCI)

Digital Video Signal Interface Format (DVSIF) Register

GPIO and DMA Control Register (GPIO_DMA_CTL)

Configures GPIO modes, clock selection, and FIFO trigger points.

I2 C Data;Control Register

Manages I²C data transfer, timing frequency, and synchronization.

Control Register Definitions-Function 1

PCI Configuration Space

PCI Configuration Registers (Header)

Details register implementation types and Vendor/Device ID for Function 1.

Vendor and Device ID Register

Command and Status Register

Interrupt Line, Interrupt Pin, Min_Gnt, Max_Lat Register

Device Control Register

Power Management Support Register

Local Registers (Memory Mapped)

Interrupt Status Register (INT_STAT)

Provides status of pending interrupt conditions for Function 1.

Interrupt Mask Register (INT_MASK)

Audio Control Register (GPIO_DMA_CTL)

Configures audio input gain, select, power-down, and edge sampling.

RISC Program Start Address Register (RISC_STRT_ADD)

Parametric Information

DC Electrical Parameters

AC Electrical Parameters

Specifies AC electrical parameters and provides timing diagrams.

Conexant Fusion 878A Specifications

General

Brand	Conexant
Model	Fusion 878A
Category	Media Converter
Language	English