Cypress Semiconductor CY7C68013A - Page 24

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document #: 38-08032 Rev. *L Page 24 of 62
55 45 30 23 5G PB5 or
FD[5]
IO/Z I
(PB5)
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB5 is a bidirectional IO port pin.
FD[5] is the bidirectional FIFO/GPIF data bus.
56 46 31 24 5F PB6 or
FD[6]
IO/Z I
(PB6)
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB6 is a bidirectional IO port pin.
FD[6] is the bidirectional FIFO/GPIF data bus.
57 47 32 25 6H PB7 or
FD[7]
IO/Z I
(PB7)
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB7 is a bidirectional IO port pin.
FD[7] is the bidirectional FIFO/GPIF data bus.
PORT C
72 57 PC0 or
GPIFADR0
IO/Z I
(PC0)
Multiplexed pin whose function is selected by
PORTCCFG.0
PC0 is a bidirectional IO port pin.
GPIFADR0 is a GPIF address output pin.
73 58 PC1 or
GPIFADR1
IO/Z I
(PC1)
Multiplexed pin whose function is selected by
PORTCCFG.1
PC1 is a bidirectional IO port pin.
GPIFADR1 is a GPIF address output pin.
74 59 PC2 or
GPIFADR2
IO/Z I
(PC2)
Multiplexed pin whose function is selected by
PORTCCFG.2
PC2 is a bidirectional IO port pin.
GPIFADR2 is a GPIF address output pin.
75 60 PC3 or
GPIFADR3
IO/Z I
(PC3)
Multiplexed pin whose function is selected by
PORTCCFG.3
PC3 is a bidirectional IO port pin.
GPIFADR3 is a GPIF address output pin.
76 61 PC4 or
GPIFADR4
IO/Z I
(PC4)
Multiplexed pin whose function is selected by
PORTCCFG.4
PC4 is a bidirectional IO port pin.
GPIFADR4 is a GPIF address output pin.
77 62 PC5 or
GPIFADR5
IO/Z I
(PC5)
Multiplexed pin whose function is selected by
PORTCCFG.5
PC5 is a bidirectional IO port pin.
GPIFADR5 is a GPIF address output pin.
78 63 PC6 or
GPIFADR6
IO/Z I
(PC6)
Multiplexed pin whose function is selected by
PORTCCFG.6
PC6 is a bidirectional IO port pin.
GPIFADR6 is a GPIF address output pin.
79 64 PC7 or
GPIFADR7
IO/Z I
(PC7)
Multiplexed pin whose function is selected by
PORTCCFG.7
PC7 is a bidirectional IO port pin.
GPIFADR7 is a GPIF address output pin.
PORT D
102 80 52 45 8A PD0 or
FD[8]
IO/Z I
(PD0)
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[8] is the bidirectional FIFO/GPIF data bus.
103 81 53 46 7A PD1 or
FD[9]
IO/Z I
(PD1)
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[9] is the bidirectional FIFO/GPIF data bus.
Table 11. FX2LP Pin Descriptions (continued)
128
TQFP
100
TQFP
56
SSOP
56
QFN
56 VF-
BGA
Name Type Default Description
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