Cypress Semiconductor CY7C68013A - Page 39

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document #: 38-08032 Rev. *L Page 39 of 62
10.3 Data Memory Read
Figure 13. Data Memory Read Timing Diagram
data in
t
CL
A[15..0]
t
AV
t
AV
RD#
t
STBL
t
STBH
t
DH
D[7..0]
data in
t
ACC1
[19]
t
DSU
Stretch = 0
Stretch = 1
t
CL
A[15..0]
t
AV
RD#
t
DH
D[7..0]
t
ACC1
t
DSU
CS#
CS#
t
SCSL
OE#
t
SOEL
CLKOUT
[17]
CLKOUT
[17]
[19]
Table 16. Data Memory Read Parameters
Parameter Description Min Typ Max Unit Notes
t
CL
1/CLKOUT Frequency 20.83 ns 48 MHz
41.66 ns 24 MHz
83.2 ns 12 MHz
t
AV
Delay from Clock to Valid Address 10.7 ns
t
STBL
Clock to RD LOW 11 ns
t
STBH
Clock to RD HIGH 11 ns
t
SCSL
Clock to CS LOW 13 ns
t
SOEL
Clock to OE LOW 11.1 ns
t
DSU
Data Setup to Clock 9.6 ns
t
DH
Data Hold Time 0 ns
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either
RD# or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for
which is based on the stretch value
Note
19. t
ACC2
and t
ACC3
are computed from the above parameters as follows:
t
ACC2
(24 MHz) = 3*t
CL
– t
AV
–t
DSU
= 106 ns
t
ACC2
(48 MHz) = 3*t
CL
– t
AV
– t
DSU
= 43 ns
t
ACC3
(24 MHz) = 5*t
CL
– t
AV
–t
DSU
= 190 ns
t
ACC3
(48 MHz) = 5*t
CL
– t
AV
– t
DSU
= 86 ns.
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