Cypress Semiconductor CY7C68013A - Page 42

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document #: 38-08032 Rev. *L Page 42 of 62
10.6 GPIF Synchronous Signals
Figure 17. GPIF Synchronous Signals Timing Diagram
[20]
DATA(output)
t
XGD
IFCLK
RDY
X
DATA(input)
valid
t
SRY
t
RYH
t
IFCLK
t
SGD
CTL
X
t
XCTL
t
DAH
N
N+1
GPIFADR[8:0]
t
SGA
Table 18. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK
[20, 21]
Parameter Description Min Max Unit
t
IFCLK
IFCLK Period 20.83 ns
t
SRY
RDY
X
to Clock Setup Time 8.9 ns
t
RYH
Clock to RDY
X
0ns
t
SGD
GPIF Data to Clock Setup Time 9.2 ns
t
DAH
GPIF Data Hold Time 0 ns
t
SGA
Clock to GPIF Address Propagation Delay 7.5 ns
t
XGD
Clock to GPIF Data Output Propagation Delay 11 ns
t
XCTL
Clock to CTL
X
Output Propagation Delay 6.7 ns
Table 19. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK
[21]
Parameter Description Min. Max. Unit
t
IFCLK
IFCLK Period
[22]
20.83 200 ns
t
SRY
RDY
X
to Clock Setup Time 2.9 ns
t
RYH
Clock to RDY
X
3.7 ns
t
SGD
GPIF Data to Clock Setup Time 3.2 ns
t
DAH
GPIF Data Hold Time 4.5 ns
t
SGA
Clock to GPIF Address Propagation Delay 11.5 ns
t
XGD
Clock to GPIF Data Output Propagation Delay 15 ns
t
XCTL
Clock to CTL
X
Output Propagation Delay 10.7 ns
Notes
20. Dashed lines denote signals with programmable polarity.
21. GPIF asynchronous RDY
x
signals have a minimum Setup time of 50 ns when using internal 48-MHz IFCLK.
22. IFCLK must not exceed 48 MHz.
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