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Introduces the CYW43455 single-chip device, its integration, and application.
Lists the various wireless and security standards supported by the CYW43455 device.
Describes the integrated regulators and power management unit (PMU) in the CYW43455.
Details the features of the Power Management Unit (PMU) integrated into the CYW43455.
Explains the power management design for the WLAN section of the CYW43455.
Details the PMU sequencer's role in system power consumption management.
Describes the low-power shutdown feature allowing the device to be turned off.
Explains control signals for managing power consumption of Bluetooth and WLAN circuits.
Explains how the CYW43455 uses an external crystal for frequency reference.
Describes using an external precision frequency reference as an alternative to a crystal.
Discusses selecting reference frequencies for the CYW43455 and auto-detection.
Details the use of a secondary low-frequency clock for low-power mode timing.
Lists the primary features of the CYW43455 Bluetooth subsystem.
Describes the integrated 2.4 GHz Bluetooth radio transceiver and its capabilities.
Lists features supported by the Bluetooth Baseband Core (BBC) for Bluetooth 4.0.
Lists features supported by the BBC for Bluetooth 4.2.
Mentions support for the Bluetooth Low Energy (BLE) operating mode.
States qualification and support for Bluetooth 5.0 mandatory features.
Describes the Link Control Layer's role in Bluetooth link control functions.
Details Bluetooth test modes and enhanced testing features for RF debugging.
Explains the Bluetooth PMU features for power management.
Describes AFH for channel assessment and channel map selection.
Discusses advanced coexistence technologies for shared antenna platforms.
Explains modes that reduce inquiry response and connection times.
Details the RAM, ROM, and patch memory sizes for the Bluetooth core.
Explains the integrated power-on reset circuit for the Bluetooth core.
Describes the slave SPI HCI transport with its physical interface signals.
Explains how transport operation is selected based on pin state during power-up.
Details the two independent PCM interfaces and their configurations.
Describes the standard 4-wire UART interface with adjustable baud rates.
Explains the I2S digital audio port support for Bluetooth audio.
Describes the integrated ARM Cortex-R4 processor, RAM, and ROM for the WLAN section.
Details the use of OTP memory for storing hardware configuration parameters.
Lists the general-purpose I/O (GPIO) pins available on the WLAN section.
Describes an interface for signaling between the device and external wireless devices.
Explains the high-speed UART interface for debugging.
Describes JTAG boundary scan and SWD mode for chip debug.
Details the SDIO v3.0 support, including UHS-I modes.
Describes the pin descriptions for the SDIO interface.
Introduces the high-performance serial I/O interconnect for PCI Express.
Explains the PCIe transaction layer for data transfer.
Describes the WLAN MAC design for high-throughput and low-power operation.
Details the WLAN Digital PHY design for wireless LAN connectivity.
Explains the wide dynamic range, direct conversion receiver.
Describes the baseband data modulation and upconversion process.
Details the dynamic and automatic on-chip calibration features.
Provides a map of the 140-ball WLBGA package.
Lists the CYW43455 pins by their pin number.
Lists the CYW43455 pins by their pin name.
Describes the signal name, type, and description of each pin.
Describes WLAN GPIO signals and strapping options for operating modes.
Details the various states and configurations of the I/O pins.
Indicates levels where permanent device damage can occur.
Shows the environmental ratings for the device.
Provides precautions for preventing ESD damage.
Lists recommended operating conditions and DC electrical characteristics.
Details the RF performance specifications for the Bluetooth receiver.
Details the RF performance specifications for the Bluetooth transmitter.
Introduces the dual-band direct conversion radio and its RF characteristics.
Provides general RF specifications for the 2.4 GHz WLAN band.
Lists receiver performance specifications for the WLAN 2.4 GHz band.
Lists transmitter performance specifications for the WLAN 2.4 GHz band.
Lists receiver performance specifications for the WLAN 5 GHz band.
Lists transmitter performance specifications for the WLAN 5 GHz band.
Provides TX and RX spurious emissions specifications for WLAN bands.
Details the electrical specifications for the core buck switching regulator.
Provides the electrical specifications for the 3.3V LDO (LDO3P3).
Lists the electrical specifications for the 2.5V LDO (BTLDO2P5).
Details the electrical specifications for the CLDO.
Provides the electrical specifications for the LNLDO.
Details the electrical specifications for the PCIe LDO.
Shows typical current consumption for the WLAN core in various modes.
Shows Bluetooth and BLE current consumption measurements.
Details the SDIO bus timing parameters for default mode.
Describes the SDIO bus timing parameters for high-speed mode.
Lists the interface parameters for PCI Express.
Details the timing characteristics for the JTAG interface.
Explains the SWD timing for read and write operations.
Describes control signals for power-up sequencing and timing.
Lists the thermal characteristics of the WLBGA package.
Explains how to estimate junction temperature using thermal parameters.
Refers to environmental characteristics data.
Provides definitions for acronyms and abbreviations used in Cypress documents.
Lists documents that may be used in conjunction with this manual.
Provides information on Cypress IoT resources for design integration.
General| Wireless LAN | 802.11 a/b/g/n/ac |
|---|---|
| Frequency Band | 2.4 GHz, 5 GHz |
| Bluetooth | Bluetooth 5.0 |
| Interface | SDIO |
| Security | WPA, WPA2 |
| Category | Single Board Computer |
