DATA PRECISION 5740 - Gating Control Mechanisms; Counter, Latch, and Display Controls

72-1002
Model 5740 COUNTER
A summary of the front panel control ma
trix is shown in Table 3-1 below.
3.3.1 Counter Gate
The Counter Gate is programmed to select
one of three inputs:
Conditioned Input (FREQUENCY MODE)
IMHz Time Base (PERIOD MODE)
Divider Output (.01 sec increments in
(SECONDS MODE) and in (EVENTS MODE)
3.3.2 Divider Gate
The Programmable Divider Gate selects
one of two inputs:
Conditioned Input (PERIOD, EVENTS
MODES)
IMHz Time Base (FREQUENCY, SECONDS
MODES)
3.4 COUNTER-LATCH-DISPLAY CONTROLS
Operation of the decimal point in the
seven-digit display is also programmed
according to the function selected by
the combined settings of slide switch SU
and rotary switch S3. A summary of
these control requirements is also in
Table 3-1.
3.4.1 Intercycle Control (Repetitive Modes)
When measuring FREQUENCY of a repeti
tive input, or the PERIOD of one cycle
of such an input, the Counter-Latch-
Display sequence is programmed by the
Intercycle Control timer. At the end of
the switch-selected time base (FREQUEN
CY) or switch-selected number of periods
(PERIOD), counter control is transferred
to the Intercycle Control circuitry
which
* Removes the input to the counter
* Transfers the counter value to the
latching register, and thence to the
display
* Resets the counter to zero
3.4.2 Manual Control
When counting SECONDS, or totalizing
EVENTS, the Counter-Latch Display is pro
grammed by the RESET-SEC/EVENTS-HOLD posi
tion of rotary switch S3. The RESET posi
tion :
* Removes the input to the counter
* Resets the counter value to zero
When operated to the SEC/EVENTS position,
the control signals:
* Enable the COUNTER Gate
* Enable the transfer from Counter to
Latch to Display
Table 3-1
MODEL 5740 COUNTER GATING CONTROL
MEASURING
FUNCTION
Input To
Counter Gate
Input To
Divider Gate
Divider
Ratio
Decimal
Point Selection
FREQUENCY
Conditioned
Input
IMHz Time
Base
Selected
GATE TIME
Per
Selection
PERIOD
IMHz Time
Base
Conditioned
Input
Selected
Numbe:" of
PRDS AVGD
SECONDS
Divider
Output
IMHz Time
Base
+ 104
=0.01 sec
Interval
DP 3
EVENTS
Divider
Output
Conditioned
Input
+ 1 None
3-4
COPYRIGHT 197S DATA PRECISION CORPORATION PRINTED IN THE U.S.A.