DATA PRECISION 5740 - Intercycle Control Operations

72-1002
Model 5740 COUNTER
cuitry. The high %aX level holds the
programmable divider in its full register
count so that the next measurement cycle
begins with the first clodk pulse or con
ditioned input pulse after removal of the
RpjAx high level input at Z19-6.
3.9 INTERCYCLE CONTROL
As shown in Figure 3-8, the Intercycle
Control consists of an intercycle oscil
lator (about 0.08 sec period), two flip-
flops connected as a counter, and three
gates that sense the counter states.
The Intercycle Control outputs: 1)
transfer the counter value to the latch
ing register, 2) reset the counter to
zero, and 3) keep the programmable divi
der at RpiAX until the display is updated
and the counter is zeroed. These out
puts are developed under control of the
intercycle oscillator when measuring
Frequency or measuring Period, or by set
tings of the rotary switch when in any
of the manual measurement modes (Seconds
or Events).
enable the Gate FF) and the next input
pulse to the divider produces a clock
pulse to the Gate FF.] The sequence of
actions initiated when the change in
Gate FF level to high state are des
cribed with reference to timing diagram
shown in Figure 3-10.
The intercycle oscillator is a relax
ation type whose period is determined by
the charging path time constant of
R31C31 ('\'.08 sec) attempting to charge
C31 to +5 volts, and the firing level of
unijunction transistor QU set by voltage
divider R32 R33 = 3V. The result is a
pulse train at TP4 of about 0.08 sec pe
riod .
The Intercycle Counter is first actu
ated by the change in level of Z21B (TJ) ,
and this change in output state produces
a high level at Z16-3, initiating the
charge cycle of the oscillator and set
ting the programmable divider to Rmax*
Succeeding changes in states of the
counter are produced by the pulse train
through Z22-11 caused by the intercycle
oscillator pulses at the Z22-11 input
(TP4).
3.9.1 Repetitive Measurement
At the end of a measurement cycle in
repetitive measuring modes, the Gate FF
receives a clock pulse from the program
mable divider Z19-1, and its level be
comes high. [It remains high until the
sense gate ZI6-3 next senses the zero-
zero state of the intercycle counter (to
The output control signals of TRANSFER
and RESET are produced in sequence as
shown in Figure 3-9.
When the Intercycle Counter reaches the
00 state, (both = 1), sense gate Z16-3
goes low, removing the constraint on Rj»iaX
of the divider. After inversion through
Z17-2, this control enables Gate FF JK,
TO"max •
I I
INTERCYCLE OSCILLATOR
,RESET
I HOLD
I SEC/EVENTS
RESET
MSD
Fig. 3-8. Model 5740 Intercycle Control, Schematic
3 8
COPYHIGHT 1»7S DATA PRECISION CORPORATION PRINTED IN THE US.A.