DATA PRECISION 5740 - Counter Gating Logic

72-1002
Model 5740 COUNTER
b) When in SEC'FREQ mode, the clock
train of IMHz pulses is the input to Z
Z19-3, and S3A and S3B determine the time
over which the frequency of the input
signal is averaged. SU establishes a
code of 1 for Divider input 2^ for all
settings , while S3 A £ B schematically
select the particular averaging, time in
terval. In manual operation, the divid
er factor is 10*^, providing a scale of
.01 seconds per count (10^ lo'+ = 102)
at the divider Time Base output Z19-1.
NOTE Rotary switch S3 is shown sche
matically in these illustrations; the
actual switch has only two wafers and uses
eight positions of a 12-position config
uration.
3.8 COUNTER GATING
Figure 3-7 illustrates the manner in
which the Counter-Latch-Display chain is
controlled in each of the four measurement
functions. As described previously, the
Counter is programmed to count either a
pulse train derived from the divided time
base (SECONDS), the IMHz time base (PERI
OD), conditioned input (FREQUENCY), or
conditioned input (EVENTS). Paragraph 3.7
has described the control over the Pro
grammable Divider, while Figure 3-7 incor
porates some aspects of Intercycle Control
programming as well as the gating to the
counter.
3.8.1 Counter Gate
The configuration of NAND gates Z15-6,
Z15-8, Z18-6 and Z18-8, inverter Z17-8
and the switches S3 and S4 comprise the
functional unit referred to previously as
the "Counter Gate" (See Figures 3-1, 3-2,
3-3 and 3-4). This counter gate deter
mines will be counted, while as shown
in Figure 3-7, the GATE FF determines when
the counter can count its input by placing
an enabling level on the first stage of
the counter high speed LSD count register.
The operation of the GATE FF is determined
by rotary switch S3 when in the manual
functions (SECONDS, EVENTS), or by the
Intercycle Control when in the repetitive
functions (FREQUENCY, PERIOD).
The Programmable Divider is set to its
maximum count in the interval between mea
surements by a high level input to termi
nal 6, Rf^iAx* This level is developed by
GATE Flip Flop Z21B and is programmed
manually by rotary switch S3 or automa
tically by the Intercycle Control cir-
Z15
P E
Z15
S F
RESET
SEC/EVENTS
Z17
SEE I.
Z18
I
INTERCYCLE
CONTROL
SEC/EVENTS
RESET
HOLD
Z21B
IMHZ CLOCK
(Z13I
ZIO
PROGRAM
DIVIDER
(Z19)
CONDITIONED
INPUT
Fig. 3-7. Model 5740 Counter Gating, Schematic
COPYRIGHT 197B DATA PRECISION CORPORATION. PRINTED IN THE U.S>.
3 7