DATA PRECISION 5740 - Time Base Generation Circuit; Programmable Divider Functionality

72-1002
Model 5740 COUNTER
Z15-2, converts the amplifier chain out
put to TTL compatible levels for Counter
or Divider processing.
3.6 TIME BASE GENERATION (FIG. 6-1)
As shown in the reference schematic,
the internal time base generator consists
of a precise crystal-controlled lOMHz
oscillator, counted down to a IMHz square
wave. The lOMHz crystal Y1, tuned by
trimmer C12 is a precision stable time
base (4ppm/year). The oscillator output
is counted down by Z23, connected for
division by 10, so that a IMHz square
wave is generated at the output Z23-12.
The Programmable Divider may have ei
ther one of two inputs, and can be pro
grammed to divide by one of four de
cades. The output, TBOUT, appears at
Pin 1. Figure 3-6 is a simplified
block diagram illustrating the manner
in which the configuration of the divi
der is established.
Input to the divider at Z19-3 is intro
duced either from Gate Z16-8 or Gate Z16-
11, which are enabled by operating slide
switch S4 to SEC-FREQ or PERIOD•EVENTS,
respectively. The countdown division
factor is determined by the combined ac
tion of rotary switch S3 and the position
of slide switch S4.
3.7 PROGRAMMABLE DIVIDER
The Programmable Divider is a monolith
ic IC device, Z19, which produces an out
put pulse (TBOUT, pin 1) for a programmed
number of input pulses at pin 3, as de
termined by the divider ratio control
signals at pins 11, 12, 13 and 14. A
control signal, Rmax? bs used to hold
the divider interval counter at its maxi
mum value so that the next input pulse
will generate an output signal.
a) When in PERIOD * EVENTS mode, the con
ditioned input signal is the input to
Z19-3, and that input is divided by a
factor according to the setting of S3.
As shown, the 2^ code is 0 for all set
tings, while switch S3 A 6 B determine
the number of averaged periods, (PERIOD
Measurement), whereas the manual settings
(HOLD-SEC/EVENTS-RESET) at switch S3C
establish code 000 for division by 10®,
thus resulting in one count for each
event.
SF
L
Z16
11
CONDITIONED
Z16
INPUT
8
f
PF
TBOUT
IN 3 Z19
"max
2^ 2^ 2'
2°
11^12
+5V
0-A/\A-
13
14;
TO COUNTER
-► TO COUNTER GATE FF
^ FROM INTERCYCLE
CONTROL
AA/\p
S3B
PERIOD-EVENTS MODE
SEC'FREOUENCY MODE
22 2' 2°
^2 2I 2®
0 0 0
1 1 0 0
10*
0 0 1
10 1 0 1
10®
0 1 0
100
1 1 0
10®
0 1 1
1000
1 1 1
10^
Fig. 3-6. Model 5740 Programmable Divider, Schematic
36
COPYRIGHT lara data precision corporation PRINTED IN THE US.A.