DATA PRECISION 5740 - Page 26

O
Table 3 2
INTERCYCLE CONTROL LOGIC STATES
MEASURE FREQUENCY or MEASURE PERIOD
o
>
-«
>
ID
a
m
o
5
z
o
o
a
s
a
>
z
H
z
m
C
>
Event Action
Flip-Flop Logic Status
COUNTER LATCH
DISPLAY
Z21A
Z20 Z21B
GATE EE
RESET
(Q-Q)-
CLOCK
TRANSFER
(Q-Q)
Q Q Q Q
Q Q
At End of Previous INTERCYCLE 0 1
0 1 0 1
JX ENABLE Ready
Latched
Static
At First CARRY Pulse out of DIVIDER
Start present Measurement Cycle
0 1
0 1 1 0
Counting
Latched
Static
At Next CARRY Pulse out of DIVIDER
End Measurement
Start Intertercycle Osc
Reset DIVIDER to Rj^y^x
1 0 0 1
0 1
Held At
Current
Count
Start
Transfer of
Counter
to Latch
Start
Display
Update
At First Intercycle Osc Pulse
0 1
1 0
1 0
Held At
Current
Count
End
Transfer
End
Display
Update
At End of Second Intercycle Osc
Pulse
1 0 1 0 1 0
RESET
To Zero Latched
Last
Meas
Updated
At End of Third Intercycle Osc
Pulse
0 1 0 1
0 1
JH ENABLE
\
\
10
I
s
10
e
a
»
ui
o
o
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