DATA PRECISION 5740 - Counter-Latch-Overflow Logic; Display Assembly Details

42 pages

Save Page as PDF

To Next Page

To Next Page

To Previous Page

To Previous Page

Loading...

72-1002

Model

5740

COUNTER

3.10

COUNTER-LATCH-OVERFLOW

The

Counter,

Latch

and

Overflow

cir

cuits

are

illustrated

in

the

reference

schematic.

The

chain

is

enabled

by

the

high

level

from

the

GATE

FF,

and

the

gated

counter

input

is

selected

as

des

cribed

in

previous

paragraphs.

The

counter

consists

of

a

hi-speed

least

significant

digit

configuration

of

dual

flip-flops

Z8

and

Z9,

followed

by

two

binary-to-BCD

counters

Z12

and

Z13

and

one

four-digit

binary-to-BCD

counter

latch,

and

multiplexer

scan

oscillator

(ZD.

The

overflow

is

determined

by

the

carry

from

Z1

that

clocks

flip-flop

Z20,

and

is

latched

in

the

combination

of

gates

Z22-6,

Z22-8,

and

inverters

Z17-10

and

Z17-12.

The

Hi-Speed

LSD

counter

utilizes

a

gating

combination

of

flip-flop

outputs

to

convert

the

sequence

to

the

valid

BCD

code

and

a

carry

at

each

tenth

count.

Figure

3-10

illustrates

the

timing

and

gating

performed

by

the

Binary-to-BCD

conversion

block

in

the

least

signifi

cant

digit.

Counters

Z12

and

Z13

are

integrated

circuits

that

incorporate

the

required

binary-to-BCD

conversion.

Individual

latches

Z6, Z7,

and

Z8

are

used

for

the

three

less

significant

digits,

while

the

four-decade

counter

Z1

incorporates

both

the

conversion

and

latch.

The

seven

decimal

digits

of

the

mea

sured

value

are

multiplexed

from

the

latches

and

are

transmitted

on

two

si

multaneous

lines:

one

line

carries

the

BCD

value

of

the

three

less

significant

digits,

while

the

other

carries

the

four

more

significant

ones.

The

multiplexing

digit

address

is

carried

on

independent

lines,

and

one

line

is

used

to

identify

one

of

the

three

lesser

and

one

of

the

four

more

significant

digits

in

the

mea

sured

value.

Transfer

to

the

latches

is

enabled

by

a

control

signal

from

ZD-6

whose

gen

eration

has

been

described

earlier.

Re

setting

the

counter

requires

two

differ

ent

levels:

a

low

level

enabling

signal

for

the

three

less

significant

digits,

and

a

high

level

for

the

enabling

action

in

Z1

for

the

four

more

significant

dig

its.

The

output

of

Z14-8

is

the

re

quired

low

level,

while

the

inversion

^'^rough

Z17-6

provides

the

necessary

high

level

for

Zl.

When

an

overflow

of

the

counter

occurs,

it

is

sensed

in

flip-flop

Z20

and

held

there

until

it

is

transferred

to

the

dis

play

by

gating

action

of

the

TRANSFER

sig

nal

from

ZD-6.

The

RESET

control

signal

returns

Z20

to

the

zero

state.

3.11

DISPLAY

The

display

assembly

is

constructed

on

a

separate

PC

board,

and,

as

shown

in

the

Z10-8

Z10-6

Z9

8

"2"

"4"

Z9

6

Z22-3

"8"

Fig.

3-10.

Model

5740

High

Speed

LSD

Timing

Waveforms

COPYRIGHT

197S

DATA

PRECISION

CORPORATION.

PRINTED

IN

THE

US.A.

3-11