Dataradio Integra-TR - Page 67

6-4
Part No. 001-4008-101/102
Figure 6-1 Logic Board Block Diagram
BI-COLO
R
LED
RS-232
DRIVE
R
DE9
DE9
SETUP
PORT
USER
PORT
U15
U21
PERIPHERAL
PA0-PA7
SIO-A
Q3
Q4
OUT
OUT-2
U17
CPU
MEM.
DECODE
U20A,B
ROM
U22
RAM
U18
A
/D
U4
CONTROL BUS
DATA BUS
ADDRESS BUS
CLK,DATA
SELECT
SIO-B
U16
TXC
TXD
CLOCK
RXC
CPLD
MODEM
RXD
MODE
SPEED
RADIO
MODULE
TXA
FILTER
CLOCK
RXS
SLICER
LEVEL
RX-EN
U1B
U5D
E-POT
U3A
RX GAIN
RXA
U5C
E-POT
U9D
WARP
U5B
E-POT
U9B
DEV
U5A
E-POT
U7B
TXA
U8A
U10
U8B
RSSI
U1A
U1D
PEAK
DETECT
U3C,D,B
U1C
FAST PEAK DETECT
TX-EN
TX ENABLE
RX-EN
RX ENABLE
SYNTH
SYNTHESIZER ENABLE-CLOCK-DATA
RESET
U19
X
1
19.6MHz
CD
CARRIER DETECT
EXT 1
EXT 2
DIAG
U7A
TEMPERATURE
U6
SENSOR
5 VOLTS
U11,U12
REGULATOR
SWB+
13.6 V
OUT
F1
REV DESCRIPTION DATE
DATARADIO INC.
Check
Draft
Design P/N
SIZE
B
SHEET
Check
DOC/N
DATE
LEVEL
INTEGRA-R
LOGIC BLOCK DIAGRAM
210-03315-000
1 / 1
990302
990302
DUNG NGUYEN
EMISSION
0