Datron 1062 - Page 51

38
FIG. 3.38 START
UP AND
NON-VOLATI
LE
RAM
PROTECTION
A6 A5 A4 A2
A1 AO
SIGNAL
M32/M16
Pin No.
Operation
0 0 0
1 X X
XKYBRD M32-2
Keyboard
read/write
0 0 1 X X X
(M32-4)
Forces
a
MPU
‘power up’
sequence
1
0 0
X X
X
(M32-11)
Triggers processor
time
guard (M43)
0
1
0
1 X X XADDT
M32-6
A-D main
counter output
enable
0
1 1 X X X
(M32-9)
Analog
interface address
latch
input
enable
0 0 0
X
0 0
XKDSPO
M16-7
\
0 0 0 X 0
1 XKDSP1 Ml
6-6
i Addresses
keyboard
0 0 0
X 1
0
XKDSP2
Ml
6-5
( I.e.d. latches
0 0 0 X
1 1 XKDSP3 M16-4
/
0 1
0
X
0 0
XADSTA
Ml
6-9
A-D, and
interrupt status output
enable
0
1
0
X
0
1 M16-10
CAL
INTERVAL switch output
enable
0
1
0
X 1
0
XADCTL
M16-1
1
A-D
control latches,
input
enable
0
1
0 X
1 1 XADDLY M16-12
A-D delay
counter input
enable
FIG. 3.39 CMOS
ADDRESS
DECODING