Datron 1062 - Page 54

41
3.
8.
3.3 A D
Measurement
Sequence
Trigger.
The
trigger,
required to
initiate the
measure-
ment
sequence,
is
generated
from
one
of three
possible
sources;
1.
Internally
generated
3/second
trigger,
from
timer
M61-7.
2.
Externally
generated
trigger,
from
EXT TRIG
on rear
panel via M24-1
3.
3. A MPU
derived
trigger from Ml
1-3 generated
when
auto-ranging,
pressing MANUAL
when
HOLD
selec-
ted,
during calibration,
an
INPUT ZERO
sequence
or
via
the
digital
interface.
The
trigger source
is selected by
the
latched data
on
M12,
enabling
one
of the
three gates
of M2.
Delay.
The trigger
pulse
clocks
the
'command latch'
MI-11
causing
the timer, M15, to
output
clock
pulses
(200Hz)
to
the delay
counters (Ml 3
and Ml
4)
after a
delay
of approx.
1.5mS set by C5,
R8, R9, R11.
The
delay
counters
proceed to
count
down to
zero,
at which
time
the delay
latch (M26)
is clocked.
Thus M26-14
becomes
a
logic
'O',
enabling the
sequencer M47
(an octal
counter) to
proceed
on to the
next step
via
M46-2.
SYNC.
The SYNC
phase
from the
sequencer
resets
the
counters
of M23
and
places
the
analog
section of the
A-D
into SIG.
The
pulse
is
fed back to M47
via
M46-3
to step
on
the
sequencer.
SIG.
During the
time that
the SIG
line
is at
logic-1
(M47-3),
the
primary counter
in M23
is enabled
and counts
out the
signal
period (20ms
in
normal mode,
or 2.5ms
superfast). When the
counter
times out,
M23-23
goes to
logic-0, enabling M47-13
via M23-14.
The
next
Master-
Clock/2 at M47-14
steps
the
sequence
on to
BIAS (M47-7
to
logic-1, M47-3
reverts to
logic-0).
BIAS. The BIAS
signal (M47-7)
is
transferred
to
the
analog
section of the
A-D by
changing the
state
of the
A
line (M38-9 to
a
logic
'0').
BIAS also enables the
secon-
dary
counter of M23
to count
out the
BIAS period (20pS).
The
signal
indicating the end of
this
period is passed
via
M46-9
causing the
sequencer to
carry on to the
next step.
The BIAS
signal also
resets the
'delay latch' (M26)
ready
for the next
measurement
cycle,
and the 'null
detector'
latch (M22A).
WAIT. The
WAIT
pulse resets
the
counter of M23
via
M39-10,
keeps the A
line to
the analog
section low,
clocks the
polarity
null
detect
latch
M22(B)
causing
a
logic
'1'
on pin
1 if the
signal applied to
the
analog section
of
the A-D
converter
was
positive (logic
'0'
if
negative)
and is
fed
back
to
enable the
sequencer via M46-3.
REF
1.
The high to low
edge of
WAIT_causes the
A
to
change state
and going
into
REF 1 makes
B a
logic
'O'.
The
analog side
is then
in the
condition to
start
'ramping
down'.
While REF 1
is high
the
primary counter
of M23
is
enabled
(pin
3)
and
counts the
period
of
REF
1.
REF 1
is ended
when a
null
detector
pulse is detected
and
latched
on to M22.
This causes
the sequencer to
step
on
once
more
from M46-3,
the
low to
high edge
from
pin
4 disabling
the
primary
counter.
REF 2.
The REF 2
signal
changes
the
state of
the A
line
(causing
the
analog
section to
ramp
down
at a
slower
rate),
resets
the
'null detect'
latch and
enables the
secondary
counter
of
M23
(Pin
13)
to
count
the
period
of
REF
2.
If the
secondary
counter
overflows,
the
primary
counter
is
incremented
from M23-16.
As
in REF
1,
a
null detector
pulse
causes the
counting
period to
end (M22-12)
and
increments
the
sequencer
via M46-3
causing
the A
and
B lines to
change state.
END.
The low to
high
edge
from M47-10
is fed
back
to
M47,
via
M48-6
giving a
master
reset. Thus the
sequencer
is
placed
into RESET.
RESET.
The sequence
pulse
from
M47-2
clocks the
'data
ready'
latch Ml
-3
placing a
signal on to
the CMOS
Data Bus
via
tri-state
buffer M10
indicating
to
the MPU
that
a
reading
is ready to
be
taken
from
the
main
counter
M23.
Data
is extracted
from the
counters
in three
bytes
(controlled by
the
A1 and AO
lines of the processor
address
bus)
with the counter
output
buffers, M24 and M25
being
enabled by
XADDT,
a decoded
processor
address.
The RESET
signal is also passed
to the
analog section
of the A-D by
changing the state
of the C
line.
Once
the
data
has been
extracted
from the
main
counter the
set-up
procedure is then
repeated
to
await
a
further
trigger.
3.8.3.4
Master Clock
and
Line
Locking
(430329
sheet 4)
To
give
improved
rejection
of line
frequency
related
noise,
the
1061
is linelocked.
The
line
frequency is
sampled
and
compared to
the
internal
master clock.
Synchronisation
is
achieved by
adjusting
the
master
clock
frequency.
A
sinusoidal
line
frequency
signal
from
the 5V
mains
tap
is
converted to a
square-wave
(M25-13)
and
-;-2(M26-1)
before being
fed
to
the
comparator
section
of
the
ULA
M23
(sheet 3).
The
MASTER CLOCK
~2
signal
is fed to
ripple
counter
M27
which
outputs a
signal
of twice
the
estimated
line
frequency,
for
line
related
periods, con-
trolled by
the ULA
(M23-18).
This
signal is
fed
to M23-19
(via
inverter
M39)
and
after a
further
-
2
,
is
compared
with
the
actual
line
frequency
(see
Fig 3.44).
The ULA
determines
whether
the
master
clock
is
running too
slow or too
fast,
producing a
signal on
pin 20
whose
pulse-width
is
proportional to
the
difference.
The
output
of pin
21 is a
25Hz
square-wave
which is
fed
to
the
up/down
input
of
counters
M41/50. Thus
depending on
the
position
and down
period of
the
pulse, the
count
held
is
increased or
decreased.