DEC VT220 - Page 100

This process repeats for all characters being DMA'ed into the line
buffer RAM, until the first scan line for all characters in the
screen row has been processed (DMA transaction completed). The
remaining scan lines of the data row are processed by accessing
the character address and attribute values stored in the line
buffer RAM during the DMA activity. Once all the scan lines for
the screen row have been processed, a new DMA transaction will be
used to input the next screen row for display.
The character generator
circuits.
(Figure 6-12)
consists of three main
• Access mux
•
Line buffer
• Character (CHAR) output circuit
TO
ViDEO
CONVERTER
TO/FROM
CPU LOGIC
TO
ATTRIBUTE
CiRCUITS
CHRO ,",-CHR7 H
CHAR
OUTPUT
CIRCUiT
ACCESS
MUX
CONTROLS
o AO H-A3 H
~~~M ~ ,l..- ..,/
LOGiC lJ
ADO H-AD7 H
FROM iAL T SEL)
ATTRIBUTE
--------1
C1RCUITS L..- __ ,j
FROM ,.-----...1'\
9007 SCO H-SC3 H
FRorv
1
TiMiNG TIMING
G EN 1-.----..;;...,--1
FROM I
QUART \ BNKSO H-BNKSl H
I .
I
I
FROM
8051 CPU '-- __ ---,
FROM
ATTRIBUTE
RAM
..... -----1
FROM
SCREEN RAM 1..- -1
Figure 6-12 Character Generator Block Diagram
6-16