DEC VT220 - Page 103

• Line buffer RAM -- is a 2K X 8-bit wide RAM device that
provides for storage and processing of the following
character address data and attribute values:
• A0-A7 inputs define the 8-bit position into which
character address or attribute data will be loaded;
•
A8 input (ATR/CHR)
(ATR/CHR
high) or
being loaded;
defines character address data
attribute value (ATR/CHR low) is
• A9-Al0 inputs define one of four banks of memory
space, each bank containing 512 bytes of memory space
for character address and attribute values (256 bytes
for each).
Figure 6-14 also shows the data input buffers which consist of two
latch devices.
• Attribute latch is used during DMA transactions to
transfer attribute values to the line buffer RAM and to
provide the attribute values to the attribute circuits
for the first scan line of the screen row undergoing DMA.
•
Character
transfer
and to
character
screen row
latch is used during DMA transactions to
character address data to the line buffer RAM
provide the character address data to tne
output circuit for the first scan line of the
undergoing DMA.
Loading character address and attribute values into the line
buffer RAM is enabled by SYNC DMA H high, LBF WR L low, and LBF
DISABLE H
low. During read out of character address and attribute
values, SYNC DMA Hand LBF DISABLE H are both lows. LBF DISABLE H
is only high when the CPU logic is accessing the alternate
character generator in the character output circuit.
Figure 6-15 provides a memory map of the line buffer RAM. Figure
6-16 shows the attribute and character latches. Later in this
chapter, Table 6-2 describes the signals shown in Figure 6-16.
6-19