DEC VT220 - Page 105

6.2.4.3 Character Output Circuit -- The character output circuit
generates the dot matrix character pattern used for the display.
The character output circuit (Figure 6-17) consists of the
following components.
• Character latch 2 provides address of character
positio~ being accessed by character latch 1 (for
processIng of the first scan line of a character address
being transferred to the line buffer RAM during DMA
transaction), line buffer RAM (during processing of
second and sUbsequent scan lines of a stored screen row) ,
or by the CPU logic (for read/write access of character
generators) •
•
Address mux -- provides address of scan line of character
being addressed by character latch 2 input, from either
the 9007 VPAC input (during scan line processing), or
from the CPU logic (during accessing the character
generators) •
•
Read/write buffer -- provides for data transfer between
the character generators (ROM and RAM) and the CPU
logic.
TOiFROM
CPU
LOGIC
TO
VIDEO
CONVERTER
FROM
9007
SCO H-SC3 H
ADDRESS
MUX
AO H-A3 H
EN CHRGEN RW H
FROM
CPU
WR L
LOGrC
EN CHRGEN L
RDL
CHRG SEL H
FROM
ALT SEl H
ACCESS
MUX
CHAR
CHAR
FROM
IADDRESS DATA!
LATCH
GEN
LINE
2 ROM
BUFFER
OE
FROM
T5L
TIMiNG
R73
GEN
NOTE
WRITE
LINES FROM READ,WRITE BUFFER ARE SAME LINES AS CHROH- CHR7H
THEY ARE illUSTRATED SEPARATELY FOR CLARITY OF BUFFER FUNCTION
Figure 6-17 Character Output Circuits Block Diagram
6-21