DEC VT220 - Page 113

The piS converter (Figure 6-26) circuit consists of the following
components.
•
Shift register --
serially shifts
when INH input
serial latch.
loads parallel data on CHR LD L low,and
data through on each DOT CLK H input,
is low. It also outputs shifted data to
• SIN latch initiates serial shifting by loading bit 0
of the parallel dot matrix data into the serial input of
the piS converter.
• Serial latch -- performs dot stretching by feeding back
the output developed from the shift register input to add
a high output to the gate at the trailing edge of each
high input (either for a single high input from the shift
register, or at the end of a series of high inputs).
The outputs from the serial latch are gated with the underline
attribute (UL ATR H) to provide all high output to video output
circuit during processing of the ninth scan line of a data row
when underline attribute is selected.
Later in this
Figure 6-26.
chapter, Table 6-2 describes the signals shown in
(SERIAL
DATAi TO
)Q- __ ViDEO
I'"-M-L-..- OUT PUT
UL t,TP H
CHRO H
FROM
CHAR
GEN
FROM
ATTRIBUTE --,
CIRCUJTS
FROM
TIMiNG DOT eLk H !
GEN
FROM {ICLR
BLA~K" CBLANKe
CIRCU" S l -C-HR-. -----+-~_L_J
FROM {
CO~VERSION ....J
CONTRO,. ..
• SHARES SAME PHYSICAL COMPONENT ILS174 LATCH I
AS
LATCH IN TiMING GENERATOR
Figure 6-26 P-S Conversion Block Diagram
6-29