Figure 14. Memory Socket Locations
Memory channels are organized as follows:
Processor 1 channel 0: slots A1, A5, and A9
channel 1: slots A2, A6, and A10
channel 2: slots A3, A7, and A11
channel 3: slots A4, A8, and A12
channel 0: slots B1, B5, and B9
channel 1: slots B2, B6, and B10
channel 2: slots B3, B7, and B11
channel 3: slots B4, B8, and B12
Processor 2 channel 0: slots C1, C5, and C9
channel 1: slots C2, C6, and C10
channel 2: slots C3, B7, and C11
channel 3: slots C4, C8, and C12
channel 0: slots D1, D5, and D9
channel 1: slots D2, D6, and D10
channel 2: slots D3, D7, and D11
channel 3: slots D4, D8, and D12
Processor 3 channel 0: slots E1, E5, and E9
channel 1: slots E2, E6, and E10
41
To Next Page
Loading...
